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152 | 152 |
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153 | 153 | #define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0)
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154 | 154 | #define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1)
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| 155 | +#define SPI1_NSS_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 2) |
| 156 | +#define SPI1_NSS_PB0_3 CH32V00X_PINMUX_DEFINE(PB, 0, SPI1, 3) |
| 157 | +#define SPI1_NSS_PD3_4 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 4) |
| 158 | +#define SPI1_NSS_PC1_5 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 5) |
| 159 | +#define SPI1_NSS_PC4_6 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 6) |
155 | 160 | #define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0)
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156 | 161 | #define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1)
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| 162 | +#define SPI1_SCK_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, SPI1, 2) |
| 163 | +#define SPI1_SCK_PB1_3 CH32V00X_PINMUX_DEFINE(PB, 1, SPI1, 3) |
| 164 | +#define SPI1_SCK_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, SPI1, 4) |
| 165 | +#define SPI1_SCK_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, SPI1, 5) |
| 166 | +#define SPI1_SCK_PB5_6 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 6) |
157 | 167 | #define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0)
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158 | 168 | #define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1)
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| 169 | +#define SPI1_MISO_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, SPI1, 2) |
| 170 | +#define SPI1_MISO_PB2_3 CH32V00X_PINMUX_DEFINE(PB, 2, SPI1, 3) |
| 171 | +#define SPI1_MISO_PD5_4 CH32V00X_PINMUX_DEFINE(PD, 5, SPI1, 4) |
| 172 | +#define SPI1_MISO_PB5_5 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 5) |
| 173 | +#define SPI1_MISO_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 6) |
159 | 174 | #define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0)
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160 | 175 | #define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1)
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| 176 | +#define SPI1_MOSI_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 2) |
| 177 | +#define SPI1_MOSI_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 3) |
| 178 | +#define SPI1_MOSI_PD6_4 CH32V00X_PINMUX_DEFINE(PD, 6, SPI1, 4) |
| 179 | +#define SPI1_MOSI_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, SPI1, 5) |
| 180 | +#define SPI1_MOSI_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, SPI1, 6) |
161 | 181 |
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162 | 182 | #define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0)
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163 | 183 | #define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1)
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