soc: nrf54h: Configure CTRLSEL and pin for TRACE

Configure the CTRLSEL value and the clock pin so that the TRACE pins
work when the TDD gets used.

Signed-off-by: Karsten Koenig <[email protected]>

Author: karstenkoenig

soc/nordic/nrf54h/soc.c

@@ -22,6 +22,7 @@
 #include <soc/nrfx_coredep.h>
 #include <soc_lrcconf.h>
 #include <dmm.h>
+#include <uicr/uicr.h>
 
 #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
 #include <nrf_ironside/cpuconf.h>
@@ -183,6 +184,13 @@ void soc_late_init_hook(void)
 
 	err_tdd = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT);
 	__ASSERT(err_tdd == 0, "err_tdd was %d", err_tdd);
+
+	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 3, GPIO_PIN_CNF_CTRLSEL_TND);
+	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 4, GPIO_PIN_CNF_CTRLSEL_TND);
+	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 5, GPIO_PIN_CNF_CTRLSEL_TND);
+	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 6, GPIO_PIN_CNF_CTRLSEL_TND);
+	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 7, GPIO_PIN_CNF_CTRLSEL_TND);
+
 #endif
 
 #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)