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Phuc Phamtiennguyenzg
Phuc Pham
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tiennguyenzg
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drivers: adc: Add ADC support for Renesas RZ/A3UL, T2M, N2L, V2L
Add ADC driver support for Renesas RZ/A3UL, T2M, N2L, V2L Signed-off-by: Phuc Pham <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
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+167
-40
lines changed

5 files changed

+167
-40
lines changed

‎drivers/adc/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU adc_mcux_gau_adc.c)
6161
zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c)
6262
zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA adc_renesas_ra.c)
6363
zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RZ adc_renesas_rz.c)
64+
zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RZ_ADC_C adc_renesas_rz.c)
6465
zephyr_library_sources_ifdef(CONFIG_ADC_MAX32 adc_max32.c)
6566
zephyr_library_sources_ifdef(CONFIG_ADC_AD4114 adc_ad4114.c)
6667
zephyr_library_sources_ifdef(CONFIG_ADC_AD7124 adc_ad7124.c)

‎drivers/adc/Kconfig.renesas_rz

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# Renesas RZ Family
22

3-
# Copyright (c) 2024 Renesas Electronics Corporation
3+
# Copyright (c) 2024-2025 Renesas Electronics Corporation
44
# SPDX-License-Identifier: Apache-2.0
55

66
config ADC_RENESAS_RZ
@@ -10,3 +10,11 @@ config ADC_RENESAS_RZ
1010
select USE_RZ_FSP_ADC
1111
help
1212
Enable the RZ ADC driver.
13+
14+
config ADC_RENESAS_RZ_ADC_C
15+
bool "Renesas RZ ADC-C Driver"
16+
default y
17+
depends on DT_HAS_RENESAS_RZ_ADC_C_ENABLED
18+
select USE_RZ_FSP_ADC
19+
help
20+
Enable the RZ ADC-C driver.

‎drivers/adc/adc_renesas_rz.c

Lines changed: 121 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2024 Renesas Electronics Corporation
2+
* Copyright (c) 2024-2025 Renesas Electronics Corporation
33
* SPDX-License-Identifier: Apache-2.0
44
*/
55

@@ -8,16 +8,27 @@
88
#include <zephyr/drivers/adc.h>
99
#include <zephyr/irq.h>
1010
#include <zephyr/logging/log.h>
11-
#include "r_adc_c.h"
11+
#include <zephyr/devicetree.h>
1212

13-
LOG_MODULE_REGISTER(adc_renesas_rz, CONFIG_ADC_LOG_LEVEL);
13+
#if defined(CONFIG_ADC_RENESAS_RZ_ADC_C)
14+
#include "r_adc_c.h"
15+
typedef adc_c_channel_cfg_t adc_channel_cfg_t;
16+
typedef adc_c_instance_ctrl_t adc_instance_ctrl_t;
17+
typedef adc_c_extended_cfg_t adc_extended_cfg_t;
18+
void adc_c_scan_end_isr(void *irq);
19+
#define ADC_SCAN_END_ISR adc_c_scan_end_isr
20+
#else /* CONFIG_ADC_RENESAS_RZ */
21+
#include "r_adc.h"
22+
void adc_scan_end_isr(void *irq);
23+
#define ADC_SCAN_END_ISR adc_scan_end_isr
24+
#endif
1425

1526
#define ADC_CONTEXT_USES_KERNEL_TIMER
1627
#include "adc_context.h"
1728

1829
#define ADC_RZ_MAX_RESOLUTION 12
1930

20-
void adc_c_scan_end_isr(void);
31+
LOG_MODULE_REGISTER(adc_renesas_rz, CONFIG_ADC_LOG_LEVEL);
2132

2233
/**
2334
* @brief RZ ADC config
@@ -42,11 +53,11 @@ struct adc_rz_data {
4253
/** Pointer to RZ ADC own device structure */
4354
const struct device *dev;
4455
/** Structure that handle fsp ADC */
45-
adc_c_instance_ctrl_t fsp_ctrl;
56+
adc_instance_ctrl_t fsp_ctrl;
4657
/** Structure that handle fsp ADC config */
4758
struct st_adc_cfg fsp_cfg;
4859
/** Structure that handle fsp ADC channel config */
49-
adc_c_channel_cfg_t fsp_channel_cfg;
60+
adc_channel_cfg_t fsp_channel_cfg;
5061
/** Pointer to memory where next sample will be written */
5162
uint16_t *buf;
5263
/** Mask with channels that will be sampled */
@@ -133,7 +144,7 @@ static void adc_rz_isr(const struct device *dev)
133144
}
134145
channels = channels >> 1;
135146
}
136-
adc_c_scan_end_isr();
147+
ADC_SCAN_END_ISR((void *)data->fsp_cfg.scan_end_irq);
137148
adc_context_on_sampling_done(&data->ctx, dev);
138149
}
139150

@@ -303,18 +314,9 @@ static int adc_rz_init(const struct device *dev)
303314
* ************************* DRIVER REGISTER SECTION ***************************
304315
*/
305316

306-
#define ADC_RZG_IRQ_CONNECT(idx, irq_name, isr) \
307-
do { \
308-
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, irq_name, irq), \
309-
DT_INST_IRQ_BY_NAME(idx, irq_name, priority), isr, \
310-
DEVICE_DT_INST_GET(idx), 0); \
311-
irq_enable(DT_INST_IRQ_BY_NAME(idx, irq_name, irq)); \
312-
} while (0)
313-
314-
#define ADC_RZG_CONFIG_FUNC(idx) ADC_RZG_IRQ_CONNECT(idx, scanend, adc_rz_isr);
315-
316-
#define ADC_RZG_INIT(idx) \
317-
static const adc_c_extended_cfg_t g_adc##idx##_cfg_extend = { \
317+
#if defined(CONFIG_ADC_RENESAS_RZ_ADC_C)
318+
#define ADC_RZ_EXTENDED_FSP_CFG(idx) \
319+
static const adc_extended_cfg_t g_adc##idx##_cfg_extend = { \
318320
.trigger_mode = ADC_C_TRIGGER_MODE_SOFTWARE, \
319321
.trigger_source = ADC_C_ACTIVE_TRIGGER_EXTERNAL, \
320322
.trigger_edge = ADC_C_TRIGGER_EDGE_FALLING, \
@@ -324,43 +326,123 @@ static int adc_rz_init(const struct device *dev)
324326
.sampling_time = 100, \
325327
.external_trigger_filter = ADC_C_FILTER_STAGE_SETTING_DISABLE, \
326328
}; \
329+
static const struct adc_rz_config adc_rz_config_##idx = { \
330+
.channel_available_mask = DT_INST_PROP(idx, channel_available_mask), \
331+
.fsp_api = &g_adc_on_adc_c, \
332+
};
333+
334+
#define ADC_RZ_FSP_CFG(idx) \
335+
.fsp_cfg = \
336+
{ \
337+
.mode = ADC_MODE_SINGLE_SCAN, \
338+
.p_callback = NULL, \
339+
.p_context = NULL, \
340+
.p_extend = &g_adc##idx##_cfg_extend, \
341+
.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
342+
.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
343+
}, \
344+
.fsp_channel_cfg = { \
345+
.scan_mask = 0, \
346+
.interrupt_setting = ADC_C_INTERRUPT_CHANNEL_SETTING_ENABLE, \
347+
}
348+
349+
#endif /* CONFIG_ADC_RENESAS_RZ_ADC_C */
350+
351+
#if defined(CONFIG_ADC_RENESAS_RZ)
352+
#define ADC_RZ_EXTENDED_FSP_CFG(idx) \
353+
static const adc_extended_cfg_t g_adc##idx##_cfg_extend = { \
354+
.add_average_count = ADC_ADD_OFF, \
355+
.clearing = ADC_CLEAR_AFTER_READ_ON, \
356+
.trigger_group_b = ADC_TRIGGER_SYNC_ELC, \
357+
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, \
358+
.adc_start_trigger_a = ADC_ACTIVE_TRIGGER_DISABLED, \
359+
.adc_start_trigger_b = ADC_ACTIVE_TRIGGER_DISABLED, \
360+
.adc_start_trigger_c_enabled = 0, \
361+
.adc_start_trigger_c = ADC_ACTIVE_TRIGGER_DISABLED, \
362+
.adc_elc_ctrl = ADC_ELC_SINGLE_SCAN, \
363+
.window_a_irq = FSP_INVALID_VECTOR, \
364+
.window_a_ipl = BSP_IRQ_DISABLED, \
365+
.window_b_irq = FSP_INVALID_VECTOR, \
366+
.window_b_ipl = BSP_IRQ_DISABLED, \
367+
}; \
368+
static const struct adc_rz_config adc_rz_config_##idx = { \
369+
.channel_available_mask = DT_INST_PROP(idx, channel_available_mask), \
370+
.fsp_api = &g_adc_on_adc, \
371+
};
372+
373+
#define ADC_RZ_FSP_CFG(idx) \
374+
.fsp_cfg = \
375+
{ \
376+
.unit = DT_INST_PROP(idx, unit), \
377+
.mode = ADC_MODE_SINGLE_SCAN, \
378+
.resolution = ADC_RESOLUTION_12_BIT, \
379+
.alignment = (adc_alignment_t)ADC_ALIGNMENT_RIGHT, \
380+
.trigger = ADC_TRIGGER_SOFTWARE, \
381+
.p_callback = NULL, \
382+
.p_context = NULL, \
383+
.p_extend = &g_adc##idx##_cfg_extend, \
384+
.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
385+
.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
386+
.scan_end_b_irq = FSP_INVALID_VECTOR, \
387+
.scan_end_b_ipl = BSP_IRQ_DISABLED, \
388+
.scan_end_c_irq = FSP_INVALID_VECTOR, \
389+
.scan_end_c_ipl = BSP_IRQ_DISABLED, \
390+
}, \
391+
.fsp_channel_cfg = { \
392+
.scan_mask = 0, \
393+
.scan_mask_group_b = 0, \
394+
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF, \
395+
.add_mask = 0, \
396+
.sample_hold_mask = 0, \
397+
.sample_hold_states = 24, \
398+
.scan_mask_group_c = 0, \
399+
}
400+
401+
#endif /* CONFIG_ADC_RENESAS_RZ */
402+
403+
#ifdef CONFIG_CPU_CORTEX_M
404+
#define GET_IRQ_FLAGS(index) 0
405+
#else /* Cortex-A/R */
406+
#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags)
407+
#endif
408+
409+
#define ADC_RZ_IRQ_CONNECT(idx, irq_name, isr) \
410+
do { \
411+
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, irq_name, irq), \
412+
DT_INST_IRQ_BY_NAME(idx, irq_name, priority), isr, \
413+
DEVICE_DT_INST_GET(idx), GET_IRQ_FLAGS(idx)); \
414+
irq_enable(DT_INST_IRQ_BY_NAME(idx, irq_name, irq)); \
415+
} while (0)
416+
417+
#define ADC_RZ_CONFIG_FUNC(idx) ADC_RZ_IRQ_CONNECT(idx, scanend, adc_rz_isr);
418+
419+
#define ADC_RZ_INIT(idx) \
420+
ADC_RZ_EXTENDED_FSP_CFG(idx) \
327421
static DEVICE_API(adc, adc_rz_api_##idx) = { \
328422
.channel_setup = adc_rz_channel_setup, \
329423
.read = adc_rz_read, \
330424
.ref_internal = DT_INST_PROP(idx, vref_mv), \
331425
IF_ENABLED(CONFIG_ADC_ASYNC, \
332426
(.read_async = adc_rz_read_async))}; \
333-
static const struct adc_rz_config adc_rz_config_##idx = { \
334-
.channel_available_mask = DT_INST_PROP(idx, channel_available_mask), \
335-
.fsp_api = &g_adc_on_adc, \
336-
}; \
337427
static struct adc_rz_data adc_rz_data_##idx = { \
338428
ADC_CONTEXT_INIT_TIMER(adc_rz_data_##idx, ctx), \
339429
ADC_CONTEXT_INIT_LOCK(adc_rz_data_##idx, ctx), \
340430
ADC_CONTEXT_INIT_SYNC(adc_rz_data_##idx, ctx), \
341431
.dev = DEVICE_DT_INST_GET(idx), \
342-
.fsp_cfg = \
343-
{ \
344-
.mode = ADC_MODE_SINGLE_SCAN, \
345-
.p_callback = NULL, \
346-
.p_context = NULL, \
347-
.p_extend = &g_adc##idx##_cfg_extend, \
348-
.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
349-
.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
350-
}, \
351-
.fsp_channel_cfg = \
352-
{ \
353-
.scan_mask = 0, \
354-
.interrupt_setting = ADC_C_INTERRUPT_CHANNEL_SETTING_ENABLE, \
355-
}, \
432+
ADC_RZ_FSP_CFG(idx), \
356433
}; \
357434
static int adc_rz_init_##idx(const struct device *dev) \
358435
{ \
359-
ADC_RZG_CONFIG_FUNC(idx) \
436+
ADC_RZ_CONFIG_FUNC(idx) \
360437
return adc_rz_init(dev); \
361438
} \
362439
DEVICE_DT_INST_DEFINE(idx, adc_rz_init_##idx, NULL, &adc_rz_data_##idx, \
363440
&adc_rz_config_##idx, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
364441
&adc_rz_api_##idx)
365442

366-
DT_INST_FOREACH_STATUS_OKAY(ADC_RZG_INIT);
443+
DT_INST_FOREACH_STATUS_OKAY(ADC_RZ_INIT);
444+
445+
#undef DT_DRV_COMPAT
446+
#define DT_DRV_COMPAT renesas_rz_adc_c
447+
448+
DT_INST_FOREACH_STATUS_OKAY(ADC_RZ_INIT);

‎dts/bindings/adc/renesas,rz-adc-c.yaml

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
# Copyright (c) 2025 Renesas Electronics Corporation
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: "Renesas RZ ADC-C driver"
5+
6+
compatible: "renesas,rz-adc-c"
7+
8+
include: [adc-controller.yaml, pinctrl-device.yaml]
9+
10+
properties:
11+
reg:
12+
required: true
13+
14+
interrupts:
15+
required: true
16+
17+
vref-mv:
18+
type: int
19+
required: true
20+
description: Indicates the reference voltage of the ADC in mV.
21+
22+
channel-available-mask:
23+
type: int
24+
required: true
25+
description: Mask for ADC channels existed in each board
26+
27+
"#io-channel-cells":
28+
const: 1
29+
30+
io-channel-cells:
31+
- input

‎dts/bindings/adc/renesas,rz-adc.yaml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,11 @@ properties:
1919
required: true
2020
description: Indicates the reference voltage of the ADC in mV.
2121

22+
unit:
23+
type: int
24+
description: Indicates the unit number of the ADC device.
25+
required: true
26+
2227
channel-available-mask:
2328
type: int
2429
required: true

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