board: gd32e103: change cpu freq to 120M

change cpu freq to 120M

Signed-off-by: YuLong Yao <[email protected]>

Author: feilongfl

boards/arm/gd32e103v_eval/gd32e103v_eval.dts

@@ -32,10 +32,6 @@
 	};
 };
 
-&rtc {
-	status = "okay";
-};
-
 &flash0 {
 	/*
 	 * For more information, see:
@@ -54,9 +50,16 @@
 	};
 };
 
+&pll {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	prediv = <2>;
+	mul = <27>;
+};
+
 &rcc {
 	clocks = <&pll>;
-	clock-frequency = <DT_FREQ_M(72)>;
+	clock-frequency = <DT_FREQ_M(108)>;
 	ahb-prescaler = <1>;
 	apb1-prescaler = <2>;
 	apb2-prescaler = <1>;

boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig

@@ -2,7 +2,7 @@
 
 CONFIG_SOC_SERIES_GD32E1X=y
 CONFIG_SOC_GD32E103VB=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
 
 # Enable MPU
 CONFIG_ARM_MPU=y

drivers/clock_control/clock_gd32e1.c

@@ -11,14 +11,123 @@
 #include <sys/util.h>
 #include <drivers/clock_control/gd32_clock_control.h>
 #include <gd32e10x_rcu.h>
+#include <gd32e10x.h>
+
 
 #define RCC_BASE DT_REG_ADDR_BY_IDX(DT_NODELABEL(rcc), 0)
 #undef RCU_REG_VAL
 #define RCU_REG_VAL(periph)             (REG32(RCC_BASE | periph ))
 
-// todo: work here later
+static inline int gd32_clock_reset()
+{
+	/* reset the RCU clock configuration to the default reset state */
+	/* Set IRC8MEN bit */
+	RCU_CTL |= RCU_CTL_IRC8MEN;
+
+	/* Reset CFG0 and CFG1 registers */
+	RCU_CFG0 = 0x00000000U;
+	RCU_CFG1 = 0x00000000U;
+
+	/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
+	RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
+	/* disable all interrupts */
+	RCU_INT = 0x00ff0000U;
+
+	/* reset HXTALBPS bit */
+	RCU_CTL &= ~(RCU_CTL_HXTALBPS);
+
+	return 0;
+}
+
+static inline void system_clock_120m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3;
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
+
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+#ifdef HXTAL_VALUE_8M
+    /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */
+    RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10);
+#elif defined (HXTAL_VALUE_25M)
+    /* CK_PREDIV0 = (CK_HXTAL)/5 *8/10 = 4 MHz */
+    RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+#endif
+
+    /* enable PLL1 */
+    RCU_CTL |= RCU_CTL_PLL1EN;
+    /* wait till PLL1 is ready */
+    while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+static inline int gd32_clock_init()
+{
+	system_clock_120m_hxtal();
+
+	return 0;
+}
+
+/**
+ * @brief Initialize clocks for the gd32
+ *
+ * This routine is called to enable and configure the clocks and PLL
+ * of the soc on the board. It depends on the board definition.
+ * This function is called on the startup and also to restore the config
+ * when exiting for low power mode.
+ *
+ * @param dev clock device struct
+ *
+ * @return 0
+ */
 int gd32_clock_control_init(const struct device *dev)
 {
+	gd32_clock_reset();
+	gd32_clock_init();
+
 	return 0;
 }
 

dts/arm/gigadevice/e1/gd32e1.dtsi

@@ -63,7 +63,7 @@
 
 		pll: pll {
 			#clock-cells = <0>;
-			compatible = "st,stm32g4-pll-clock";
+			compatible = "gd,gd32e103-pll-clock";
 			status = "disabled";
 		};
 	};

dts/bindings/clock/gd,gd32-hse-clock.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: GD32 HSE Clock
+
+compatible: "gd,gd32-hse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    hse-bypass:
+      type: boolean
+      required: false
+      description: |
+        HSE crystal oscillator bypass
+        Set to the property to by-pass the oscillator with an external clock.

dts/bindings/clock/gd,gd32e103-pll-clock.yaml

@@ -0,0 +1,47 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
+
+  Takes one of clk_hse, pll2 or clk_hsi as input clock.
+  When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
+  pll2, configurable prescaler is used.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLLCLK) = f(PLLIN) x PLLMUL       --> SYSCLK (System Clock)
+    f(USBCLK) = f(PLLCLK) * 2 / USBPRE  --> USB
+
+    with, depending on the case:
+            f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
+            f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse or pll2
+
+  The PLL output frequency must not exceed 72 MHz.
+
+
+compatible: "gd,gd32e103-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    mul:
+      type: int
+      required: true
+      description: |
+          Configurable mul
+          Valid range: 2 - 31
+
+    prediv:
+      type: int
+      required: false
+      description: |
+          Configurable prescaler
+          Valid range: 1 - 16