Skip to content

Commit 1521cb9

Browse files
VitekSTfabiobaltieri
VitekST
authored and
fabiobaltieri
committed
soc: mimxrt798s: Expand definitions for /hifi4
Add desired Kconfig implications for the mimxrt798s/hifi4 domain. Add pinctrl_soc.h and set up an include path for it. Signed-off-by: Vit Stanicek <[email protected]>
1 parent 9e99b93 commit 1521cb9

File tree

5 files changed

+122
-0
lines changed

5 files changed

+122
-0
lines changed

‎boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4_defconfig

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
#
2+
# Copyright 2025 NXP
3+
#
4+
# SPDX-License-Identifier: Apache-2.0
5+
#
6+
7+
CONFIG_SERIAL=y
8+
CONFIG_CONSOLE=y
9+
CONFIG_UART_CONSOLE=y
10+
CONFIG_GPIO=y

‎soc/nxp/imxrt/imxrt7xx/Kconfig

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,12 @@ config SOC_MIMXRT798S_HIFI4
4646
select XTENSA_GEN_HANDLERS
4747
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
4848
select GEN_ISR_TABLES
49+
select CLOCK_CONTROL
50+
select SOC_EARLY_INIT_HOOK
51+
select NXP_INPUTMUX
4952
select HAS_MCUX
53+
select HAS_MCUX_SYSCON
54+
select HAS_MCUX_FLEXCOMM
5055

5156
config SOC_MIMXRT798S_HIFI1
5257
select XTENSA
@@ -77,4 +82,19 @@ config MCUX_CORE_SUFFIX
7782
default "_hifi4" if SOC_MIMXRT798S_HIFI4
7883
default "_hifi1" if SOC_MIMXRT798S_HIFI1
7984

85+
if SOC_MIMXRT798S_HIFI4
86+
87+
DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
88+
DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
89+
DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text)
90+
91+
config RT798_HIFI4_STACK_SIZE
92+
hex "Boot time stack size"
93+
default 0x1000
94+
help
95+
Stack space is reserved at the end of the RT798_HIFI4_DATA_MEM
96+
region, starting at RT798_HIFI4_DATA_MEM_ADDR - RT798_HIFI4_STACK_SIZE
97+
98+
endif # SOC_MIMXRT798S_HIFI4
99+
80100
endif # SOC_SERIES_IMXRT7XX

‎soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,10 @@ config GEN_IRQ_VECTOR_TABLE
5959
config NXP_IMXRT_BOOT_HEADER
6060
default n
6161

62+
# Same reasoning as above.
63+
config I2S_HAS_PLL_SETTING
64+
default n
65+
6266
endif # SOC_MIMXRT798S_HIFI4
6367

6468
if SOC_MIMXRT798S_HIFI1

‎soc/nxp/imxrt/imxrt7xx/hifi4/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,5 +5,6 @@
55
#
66

77
zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
8+
zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
89

910
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/nxp/imxrt/imxrt7xx/hifi4/pinctrl_soc.h

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,87 @@
1+
/*
2+
* Copyright 2024-2025 NXP
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
8+
#define ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
9+
10+
#include <zephyr/devicetree.h>
11+
#include <zephyr/types.h>
12+
13+
#ifdef __cplusplus
14+
extern "C" {
15+
#endif
16+
17+
/** @cond INTERNAL_HIDDEN */
18+
19+
typedef uint32_t pinctrl_soc_pin_t;
20+
21+
#define IOPCTL_PIO_PUPDENA_MASK (0x10U)
22+
#define IOPCTL_PIO_PUPDSEL_MASK (0x20U)
23+
24+
#define IOPCTL_PIO_ODENA_MASK (0x400U)
25+
#define IOPCTL_PIO_ODENA_SHIFT (10U)
26+
#define IOPCTL_PIO_ODENA(x) \
27+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK)
28+
29+
#define IOPCTL_PIO_IBENA_MASK (0x40U)
30+
#define IOPCTL_PIO_IBENA_SHIFT (6U)
31+
#define IOPCTL_PIO_IBENA(x) \
32+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK)
33+
34+
/* Please note there is no SLEWRATE attribution on IOPCTL2 */
35+
#define IOPCTL_PIO_SLEWRATE_MASK (0x80U)
36+
#define IOPCTL_PIO_SLEWRATE_SHIFT (7U)
37+
#define IOPCTL_PIO_SLEWRATE(x) \
38+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK)
39+
40+
/* Please note there is no FULLDRIVE attribution on IOPCTL2 */
41+
#define IOPCTL_PIO_FULLDRIVE_MASK (0x100U)
42+
#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U)
43+
#define IOPCTL_PIO_FULLDRIVE(x) \
44+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK)
45+
46+
#define IOPCTL_PIO_IIENA_MASK (0x800U)
47+
#define IOPCTL_PIO_IIENA_SHIFT (11U)
48+
#define IOPCTL_PIO_IIENA(x) \
49+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK)
50+
51+
/* Please note there is no AMENA attribution on IOPCTL2 */
52+
#define IOPCTL_PIO_AMENA_MASK (0x200U)
53+
#define IOPCTL_PIO_AMENA_SHIFT (9U)
54+
#define IOPCTL_PIO_AMENA(x) \
55+
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK)
56+
57+
#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \
58+
(IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
59+
(IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \
60+
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
61+
(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \
62+
IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
63+
IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
64+
IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \
65+
IOPCTL_PIO_FULLDRIVE( \
66+
DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \
67+
IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
68+
IOPCTL_PIO_AMENA( \
69+
DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
70+
71+
/* MCUX RT parts only have one pin type */
72+
#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
73+
#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
74+
#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
75+
76+
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
77+
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group),
78+
79+
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
80+
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
81+
Z_PINCTRL_STATE_PIN_INIT)}
82+
83+
#ifdef __cplusplus
84+
}
85+
#endif
86+
87+
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ */

0 commit comments

Comments
 (0)