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drivers: ethernet: eth_stm32_hal: Add stm32n6 ethernet support
- Added macros `STM32_ETH_PHY_MODE` and `STM32_ETH_SPEED` to determine the media interface type and Ethernet speed based on the `phy-connection-type` property from the device tree. - Included conditional support for `gmii` and `rgmii` only for devices compatible with `st_stm32n6_ethernet`. -Update the ETH_STM32_HAL menu configuration to conditionally select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X is enabled. -Align Ethernet descriptors to 32 bytes for STM32N6 to ensure efficient DMA operations and improve cache line efficiency and overall performance -Add RISAF configuration in eth_initialize function for STM32N6 series to set up master and slave security attributes for the Ethernet peripheral. -Ensure RISAF configuration is done before enabling the Ethernet clock to maintain proper security attributes. Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <[email protected]>
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‎drivers/ethernet/Kconfig.stm32_hal‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,11 +9,12 @@ menuconfig ETH_STM32_HAL
99
default y
1010
depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
1111
select USE_STM32_HAL_ETH
12-
select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
12+
select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X
13+
select NOCACHE_MEMORY if (SOC_SERIES_STM32H7X && CPU_CORTEX_M7)
1314
select HWINFO
1415
select ETH_DSA_SUPPORT
1516
select PINCTRL
16-
select MDIO if SOC_SERIES_STM32H5X || SOC_SERIES_STM32H7X
17+
select MDIO if SOC_SERIES_STM32H5X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32N6X
1718
imply CRC
1819
help
1920
Enable STM32 HAL based Ethernet driver. It is available for
@@ -26,7 +27,8 @@ choice ETH_STM32_HAL_API_VERSION
2627

2728
config ETH_STM32_HAL_API_V2
2829
bool "Use official STM32Cube HAL driver"
29-
depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
30+
depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X
31+
select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X
3032
help
3133
Use the official STM32Cube HAL driver instead of the legacy one.
3234

‎drivers/ethernet/eth_stm32_hal.c‎

Lines changed: 83 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,34 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
4949
#define ETH_STM32_RANDOM_MAC
5050
#endif
5151

52+
#define MAC_NODE DT_NODELABEL(mac)
53+
54+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
55+
#define STM32_ETH_PHY_MODE(node_id) \
56+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? HAL_ETH_MII_MODE : \
57+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rmii) ? HAL_ETH_RMII_MODE : \
58+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, gmii) ? HAL_ETH_GMII_MODE : \
59+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rgmii) ? HAL_ETH_RGMII_MODE : \
60+
HAL_ETH_RMII_MODE))))
61+
62+
#define STM32_ETH_SPEED(node_id) \
63+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? ETH_SPEED_100M : \
64+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rmii) ? ETH_SPEED_100M : \
65+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, gmii) ? ETH_SPEED_1000M : \
66+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rgmii) ? ETH_SPEED_1000M : \
67+
ETH_SPEED_100M))))
68+
#else
69+
#define STM32_ETH_PHY_MODE(node_id) \
70+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? HAL_ETH_MII_MODE : \
71+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rmii) ? HAL_ETH_RMII_MODE : \
72+
HAL_ETH_RMII_MODE))
73+
74+
#define STM32_ETH_SPEED(node_id) \
75+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? ETH_SPEED_100M : \
76+
(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rmii) ? ETH_SPEED_100M : \
77+
ETH_SPEED_100M))
78+
#endif
79+
5280
#if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \
5381
!DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
5482
#error DTCM for DMA buffer is activated but zephyr,dtcm is not present in dts
@@ -76,9 +104,6 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
76104
#define ETH_RXBUFNB ETH_RX_DESC_CNT
77105
#define ETH_TXBUFNB ETH_TX_DESC_CNT
78106

79-
#define ETH_MEDIA_INTERFACE_MII HAL_ETH_MII_MODE
80-
#define ETH_MEDIA_INTERFACE_RMII HAL_ETH_RMII_MODE
81-
82107
/* Only one tx_buffer is sufficient to pass only 1 dma_buffer */
83108
#define ETH_TXBUF_DEF_NB 1U
84109
#else
@@ -97,6 +122,10 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
97122
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
98123
#define __eth_stm32_desc __attribute__((section(".eth_stm32_desc")))
99124
#define __eth_stm32_buf __attribute__((section(".eth_stm32_buf")))
125+
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
126+
#define __eth_stm32_rx_desc ALIGN_32BYTES(__attribute__((section(".RxDecripSection"))))
127+
#define __eth_stm32_tx_desc ALIGN_32BYTES(__attribute__((section(".TxDecripSection"))))
128+
#define __eth_stm32_buf ALIGN_32BYTES(__attribute__((section(".eth_stm32_buf"))))
100129
#elif defined(CONFIG_NOCACHE_MEMORY)
101130
#define __eth_stm32_desc __nocache __aligned(4)
102131
#define __eth_stm32_buf __nocache __aligned(4)
@@ -105,8 +134,14 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
105134
#define __eth_stm32_buf __aligned(4)
106135
#endif
107136

137+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
138+
static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB] __eth_stm32_rx_desc;
139+
static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB] __eth_stm32_tx_desc;
140+
#else
108141
static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
109142
static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
143+
#endif
144+
110145
static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf;
111146
static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf;
112147

@@ -816,7 +851,12 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
816851
CONTAINER_OF(heth, struct eth_stm32_hal_dev_data, heth);
817852

818853
switch (error_code) {
854+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
855+
case HAL_ETH_ERROR_DMA_CH0:
856+
case HAL_ETH_ERROR_DMA_CH1:
857+
#else
819858
case HAL_ETH_ERROR_DMA:
859+
#endif
820860
dma_error = HAL_ETH_GetDMAError(heth);
821861

822862
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
@@ -913,6 +953,32 @@ static void generate_mac(uint8_t *mac_addr)
913953
#endif
914954
}
915955

956+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
957+
/**
958+
* Configures the RISAF (RIF Security Attribute Framework) for Ethernet on STM32N6.
959+
* This function sets up the master and slave security attributes for the Ethernet peripheral.
960+
*/
961+
962+
static void RISAF_Config(void)
963+
{
964+
/* Define and initialize the master configuration structure */
965+
RIMC_MasterConfig_t RIMC_master = {0};
966+
967+
/* Enable the clock for the RIFSC (RIF Security Controller) */
968+
__HAL_RCC_RIFSC_CLK_ENABLE();
969+
970+
RIMC_master.MasterCID = RIF_CID_1;
971+
RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
972+
973+
/* Configure the master attributes for the Ethernet peripheral (ETH1) */
974+
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_ETH1, &RIMC_master);
975+
976+
/* Set the secure and privileged attributes for the Ethernet peripheral (ETH1) as a slave */
977+
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_ETH1,
978+
RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
979+
}
980+
#endif
981+
916982
static int eth_initialize(const struct device *dev)
917983
{
918984
struct eth_stm32_hal_dev_data *dev_data;
@@ -936,6 +1002,11 @@ static int eth_initialize(const struct device *dev)
9361002
return -ENODEV;
9371003
}
9381004

1005+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
1006+
/* RISAF Configuration */
1007+
RISAF_Config();
1008+
#endif
1009+
9391010
/* enable clock */
9401011
ret = clock_control_on(dev_data->clock,
9411012
(clock_control_subsys_t)&cfg->pclken);
@@ -967,8 +1038,15 @@ static int eth_initialize(const struct device *dev)
9671038
heth->Init.MACAddr = dev_data->mac_addr;
9681039

9691040
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1041+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
1042+
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
1043+
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
1044+
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
1045+
}
1046+
#else
9701047
heth->Init.TxDesc = dma_tx_desc_tab;
9711048
heth->Init.RxDesc = dma_rx_desc_tab;
1049+
#endif
9721050
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
9731051
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
9741052

@@ -1025,7 +1103,7 @@ static int eth_initialize(const struct device *dev)
10251103
mac_config.DuplexMode = IS_ENABLED(CONFIG_ETH_STM32_MODE_HALFDUPLEX) ?
10261104
ETH_HALFDUPLEX_MODE : ETH_FULLDUPLEX_MODE;
10271105
mac_config.Speed = IS_ENABLED(CONFIG_ETH_STM32_SPEED_10M) ?
1028-
ETH_SPEED_10M : ETH_SPEED_100M;
1106+
ETH_SPEED_10M : STM32_ETH_SPEED(MAC_NODE);
10291107
hal_ret = HAL_ETH_SetMACConfig(heth, &mac_config);
10301108
if (hal_ret != HAL_OK) {
10311109
LOG_ERR("HAL_ETH_SetMACConfig: failed: %d", hal_ret);
@@ -1330,8 +1408,7 @@ static struct eth_stm32_hal_dev_data eth0_data = {
13301408
.ChecksumMode = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
13311409
ETH_CHECKSUM_BY_HARDWARE : ETH_CHECKSUM_BY_SOFTWARE,
13321410
#endif /* !CONFIG_SOC_SERIES_STM32H7X */
1333-
.MediaInterface = IS_ENABLED(CONFIG_ETH_STM32_HAL_MII) ?
1334-
ETH_MEDIA_INTERFACE_MII : ETH_MEDIA_INTERFACE_RMII,
1411+
.MediaInterface = STM32_ETH_PHY_MODE(MAC_NODE),
13351412
},
13361413
},
13371414
};

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