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drivers: gpio: Add driver for Aesc Silicon
Add basic support for the Aesc Silicon GPIO controller. This IP core has internal tri-states and therefore a read, write and direction registers. Additionally, it has advanced monitoring capabilities for interrupt generation; low or high leve and rising or falling edge. Interrupt support will be added later when ElemRV supports interrupt in Zephyr. Signed-off-by: Daniel Schultz <[email protected]>
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‎drivers/gpio/CMakeLists.txt‎

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@@ -8,6 +8,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_GPIO_AD559X gpio_ad559x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ADP5585 gpio_adp5585.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ADS1X4S0X gpio_ads1x4s0x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AESC gpio_aesc.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ gpio_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ANDES_ATCGPIO100 gpio_andes_atcgpio100.c)

‎drivers/gpio/Kconfig‎

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@@ -97,6 +97,7 @@ config GPIO_ENABLE_DISABLE_INTERRUPT
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source "drivers/gpio/Kconfig.ad559x"
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source "drivers/gpio/Kconfig.adp5585"
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source "drivers/gpio/Kconfig.ads1x4s0x"
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source "drivers/gpio/Kconfig.aesc"
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source "drivers/gpio/Kconfig.altera"
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source "drivers/gpio/Kconfig.ambiq"
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source "drivers/gpio/Kconfig.andes_atcgpio100"

‎drivers/gpio/Kconfig.aesc‎

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# Copyright (c) 2025 Aesc Silicon
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_AESC
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bool "Aesc Silicon GPIO driver"
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default y
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depends on DT_HAS_AESC_GPIO_ENABLED
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help
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Enable the Aesc Silicon GPIO driver.

‎drivers/gpio/gpio_aesc.c‎

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/*
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* Copyright (c) 2025 Aesc Silicon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT aesc_gpio
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#include <errno.h>
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#include <ip_identification.h>
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#include <soc.h>
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#include <zephyr/arch/common/sys_bitops.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(aesc_gpio, CONFIG_GPIO_LOG_LEVEL);
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struct gpio_aesc_config {
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DEVICE_MMIO_ROM;
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};
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struct gpio_aesc_regs {
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uint32_t info;
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uint32_t read;
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uint32_t write;
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uint32_t direction;
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uint32_t high_ip;
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uint32_t high_ie;
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uint32_t low_ip;
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uint32_t low_ie;
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uint32_t rise_ip;
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uint32_t rise_ie;
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uint32_t fall_ip;
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uint32_t fall_ie;
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} __packed;
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struct gpio_aesc_data {
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DEVICE_MMIO_RAM;
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sys_slist_t cb;
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struct k_spinlock lock;
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};
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#define DEV_CFG(dev) ((struct gpio_aesc_config *)(dev)->config)
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#define DEV_DATA(dev) ((struct gpio_aesc_data *)(dev)->data)
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#define DEV_GPIO(dev) ((struct gpio_aesc_regs *)DEVICE_MMIO_GET(dev))
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static int gpio_aesc_config(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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struct gpio_aesc_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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/* Configure gpio direction */
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if (flags & GPIO_OUTPUT) {
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gpio->direction |= BIT(pin);
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} else {
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gpio->direction &= ~BIT(pin);
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_aesc_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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*value = gpio->read;
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return 0;
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}
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static int gpio_aesc_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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struct gpio_aesc_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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gpio->write = (gpio->write & ~mask) | (value & mask);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_aesc_port_set_bits_raw(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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struct gpio_aesc_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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gpio->write |= mask;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_aesc_port_clear_bits_raw(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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struct gpio_aesc_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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gpio->write &= ~mask;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_aesc_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_aesc_regs *gpio = DEV_GPIO(dev);
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struct gpio_aesc_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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gpio->write ^= mask;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_aesc_init(const struct device *dev)
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{
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volatile uintptr_t *base_addr = (volatile uintptr_t *)DEV_GPIO(dev);
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volatile struct gpio_aesc_regs *gpio;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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LOG_DBG("IP core version: %i.%i.%i.",
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ip_id_get_major_version(base_addr),
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ip_id_get_minor_version(base_addr),
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ip_id_get_patchlevel(base_addr)
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);
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DEVICE_MMIO_GET(dev) = ip_id_relocate_driver(base_addr);
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LOG_DBG("Relocate driver to address 0x%lx.", DEVICE_MMIO_GET(dev));
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gpio = DEV_GPIO(dev);
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gpio->high_ie = 0;
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gpio->low_ie = 0;
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gpio->rise_ie = 0;
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gpio->fall_ie = 0;
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return 0;
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}
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static DEVICE_API(gpio, gpio_aesc_driver_api) = {
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.pin_configure = gpio_aesc_config,
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.port_get_raw = gpio_aesc_port_get_raw,
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.port_set_masked_raw = gpio_aesc_port_set_masked_raw,
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.port_set_bits_raw = gpio_aesc_port_set_bits_raw,
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.port_clear_bits_raw = gpio_aesc_port_clear_bits_raw,
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.port_toggle_bits = gpio_aesc_port_toggle_bits,
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};
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#define AESC_GPIO_INIT(no) \
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static struct gpio_aesc_data gpio_aesc_dev_data_##no; \
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static struct gpio_aesc_config gpio_aesc_dev_cfg_##no = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(no)), \
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}; \
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DEVICE_DT_INST_DEFINE(no, \
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gpio_aesc_init, \
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NULL, \
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&gpio_aesc_dev_data_##no, \
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&gpio_aesc_dev_cfg_##no, \
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PRE_KERNEL_2, \
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CONFIG_GPIO_INIT_PRIORITY, \
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(void *)&gpio_aesc_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AESC_GPIO_INIT)

‎dts/bindings/gpio/aesc,gpio.yaml‎

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#
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# Copyright (c) 2025 Aesc Silicon
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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title: Aesc Silicon GPIO (General Purpose Input/Output)
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description: |
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The GPIO (General-Purpose Input/Output) IP Core with tri-state pins is a digital interface
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that allows each pin to be configured as either an input or an output, with additional control
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for setting the direction of data flow.
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compatible: "aesc,gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

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