Skip to content

Commit 164bbdf

Browse files
jerome-pouillerkartben
authored andcommitted
drivers: dma: siwx91x: Use DT to declare descriptors
Silabs siwx91x hardware use specific memory areas to store descriptors for DMA requests. These areas are tightly coupled between the CPU and the hardware. This helps in reducing the wait cycles. Until now these addresses was also hard coded in the DT and in the linker script. This patch leverage the zephyr,memory-region driver to centralize the information in the DT. Then, with this new implementation, the memory mapping is easier to understand for the reader. Signed-off-by: Jérôme Pouiller <[email protected]>
1 parent 95ac568 commit 164bbdf

File tree

4 files changed

+23
-29
lines changed

4 files changed

+23
-29
lines changed

drivers/dma/dma_silabs_siwx91x.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -670,7 +670,7 @@ static DEVICE_API(dma, siwx91x_dma_api) = {
670670
.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \
671671
.reg = (UDMA0_Type *)DT_INST_REG_ADDR(inst), \
672672
.irq_number = DT_INST_PROP_BY_IDX(inst, interrupts, 0), \
673-
.sram_desc_addr = (RSI_UDMA_DESC_T *)DT_INST_PROP(inst, silabs_sram_desc_addr), \
673+
.sram_desc_addr = DT_REG_ADDR(DT_INST_PHANDLE(inst, silabs_sram_region)), \
674674
.irq_configure = siwx91x_dma_irq_configure_##inst, \
675675
}; \
676676
DEVICE_DT_INST_DEFINE(inst, &siwx91x_dma_init, NULL, &dma_data_##inst, &dma_cfg_##inst, \

dts/arm/silabs/siwg917.dtsi

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
#include <arm/armv7-m.dtsi>
88
#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
9+
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
910
#include <freq.h>
1011

1112
/ {
@@ -27,9 +28,24 @@
2728

2829
sram0: memory@0 {
2930
compatible = "mmio-sram";
31+
/* remove sram_dma0 region at the end of the sram */
3032
reg = <0x00000000 DT_SIZE_K(191)>;
3133
};
3234

35+
sram_dma0: memory-dma@2fc00 {
36+
compatible = "zephyr,memory-region", "mmio-sram";
37+
reg = <0x0002fc00 DT_SIZE_K(1)>;
38+
zephyr,memory-region = "dma0";
39+
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
40+
};
41+
42+
sram_dma1: memory-dma@24061c00 {
43+
compatible = "zephyr,memory-region", "mmio-sram";
44+
reg = <0x24061c00 DT_SIZE_K(1)>;
45+
zephyr,memory-region = "dma1";
46+
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
47+
};
48+
3349
bt_hci0: bt_hci {
3450
compatible = "silabs,siwx91x-bt-hci";
3551
status = "disabled";
@@ -243,7 +259,7 @@
243259
interrupts = <33 0>;
244260
interrupt-names = "dma0";
245261
clocks = <&clock0 SIWX91X_CLK_DMA0>;
246-
silabs,sram-desc-addr = <0x2fc00>;
262+
silabs,sram-region = <&sram_dma0>;
247263
#dma-cells = < 1>;
248264
dma-channels = <32>;
249265
status = "disabled";
@@ -257,7 +273,7 @@
257273
interrupts = <10 0>;
258274
interrupt-names = "ulpdma";
259275
clocks = <&clock0 SIWX91X_CLK_ULP_DMA>;
260-
silabs,sram-desc-addr = <0x24061c00>;
276+
silabs,sram-region = <&sram_dma1>;
261277
#dma-cells = < 1>;
262278
dma-channels = <12>;
263279
status = "disabled";

dts/bindings/dma/silabs,siwx91x-dma.yaml

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,12 @@ properties:
88
reg:
99
required: true
1010

11-
silabs,sram-desc-addr:
12-
type: int
11+
silabs,sram-region:
12+
type: phandle
1313
required: true
1414
description: |
15-
SRAM Address for UDMA Descriptor Storage. This address must correspond to the location
16-
of the udma_addr0 section in the linker script for the dma0 node, and the udma_addr1
17-
section for the ulpdma node. Ensure that the value specified for the SRAM address matches
18-
the respective section defined in the linker file for each UDMA node, as this alignment
19-
is critical for proper descriptor management and data transfer.
15+
SRAM Address for UDMA Descriptor Storage. This address must match to the
16+
location used by the hardware.
2017
2118
"#dma-cells":
2219
const: 1

soc/silabs/silabs_siwx91x/siwg917/linker.ld

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -5,29 +5,10 @@
55
*/
66
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
77

8-
MEMORY
9-
{
10-
udma0 (rwx) : ORIGIN = 0x0002fc00, LENGTH = 0x00000400
11-
udma1 (rwx) : ORIGIN = 0x24061c00, LENGTH = 0x00000400
12-
}
13-
148
SECTIONS
159
{
1610
.common_tcm_code :
1711
{
1812
*(.common_tcm_code*)
1913
} > FLASH
20-
21-
/* These regions of SRAM is where the UDMA descriptors are stored. The corresponding
22-
section must be properly declared in the linker script to ensure correct data transfer
23-
and proper functioning of the UDMA module */
24-
.udma_addr0 :
25-
{
26-
*(.udma_addr0*)
27-
} > udma0 AT> FLASH
28-
29-
.udma_addr1 :
30-
{
31-
*(.udma_addr1*)
32-
} > udma1 AT> FLASH
3314
}

0 commit comments

Comments
 (0)