drivers: pm_cpu_ops: Add ARM FVP CPU power management driver

Nicolas Pitre · Nicolas Pitre · commit 1665922ed3b2 · 2025-10-02T07:16:13.000-04:00
Add a new PM CPU ops driver for ARM Fixed Virtual Platform (FVP) that
enables bare metal SMP support without ARM Trusted Firmware (ATF).

The driver provides CPU power-on and system reset operations by directly
interfacing with FVP's power controller (PWRC) and V2M system registers.

The implementation includes RVBAR_EL3 configuration to redirect
secondary CPU reset vectors to Zephyr's image header, enabling
proper SMP initialization without firmware assistance.

Signed-off-by: Nicolas Pitre &lt;npitre@baylibre.com&gt;
diff --git a/boards/arm/fvp_base_revc_2xaemv8a/board.cmake b/boards/arm/fvp_base_revc_2xaemv8a/board.cmake
@@ -43,4 +43,12 @@ if(CONFIG_BUILD_WITH_TFA)
     set(FVP_FLASH_FILE ${TFA_BINARY_DIR}/fvp/release/fip.bin)
   endif()
 
+elseif(CONFIG_PM_CPU_OPS_FVP)
+  # Configure RVBAR_EL3 for bare metal SMP when using FVP PM CPU ops driver
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+    # Set RVBAR_EL3 for secondary CPUs to Zephyr image base address
+    -C cluster0.cpu1.RVBAR=${CONFIG_KERNEL_VM_BASE}
+    -C cluster0.cpu2.RVBAR=${CONFIG_KERNEL_VM_BASE}
+    -C cluster0.cpu3.RVBAR=${CONFIG_KERNEL_VM_BASE}
+    )
 endif()
diff --git a/drivers/pm_cpu_ops/CMakeLists.txt b/drivers/pm_cpu_ops/CMakeLists.txt
@@ -6,4 +6,6 @@ zephyr_library_sources_ifdef(CONFIG_PM_CPU_OPS pm_cpu_ops_weak_impl.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM_CPU_OPS_PSCI pm_cpu_ops_psci.c)
 
+zephyr_library_sources_ifdef(CONFIG_PM_CPU_OPS_FVP pm_cpu_ops_fvp.c)
+
 zephyr_library_sources_ifdef(CONFIG_PSCI_SHELL psci_shell.c)
diff --git a/drivers/pm_cpu_ops/Kconfig b/drivers/pm_cpu_ops/Kconfig
@@ -30,6 +30,17 @@ config PM_CPU_OPS_PSCI
 	  0022A ("Power State Coordination Interface System Software on
 	  ARM processors").
 
+config PM_CPU_OPS_FVP
+	bool "Support for ARM FVP CPU power management"
+	depends on DT_HAS_ARM_FVP_PWRC_ENABLED && !PM_CPU_OPS_PSCI
+	default y if SMP
+	select PM_CPU_OPS_HAS_DRIVER
+	help
+	  Say Y here if you want Zephyr to support CPU power management
+	  operations on ARM Fixed Virtual Platform (FVP) without PSCI.
+	  This driver directly controls the FVP power controller and
+	  V2M system registers for CPU power-on and system reset operations.
+
 config PSCI_SHELL
 	bool "Support for PSCI interface shell commands"
 	depends on SHELL && PM_CPU_OPS_PSCI
diff --git a/drivers/pm_cpu_ops/pm_cpu_ops_fvp.c b/drivers/pm_cpu_ops/pm_cpu_ops_fvp.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT arm_fvp_pwrc
+
+#define LOG_LEVEL CONFIG_PM_CPU_OPS_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(fvp_pm_cpu_ops);
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pm_cpu_ops.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/devicetree.h>
+
+/* FVP Platform Constants */
+#define FVP_PWRC_BASE			DT_INST_REG_ADDR(0)
+#define FVP_V2M_SYSREGS_BASE		DT_REG_ADDR(DT_INST_PHANDLE(0, arm_vexpress_sysreg))
+
+/* FVP Power Controller Register Offsets */
+#define PWRC_PPONR_OFF		0x4	/* Power-on Request */
+#define PWRC_PSYSR_OFF		0x10	/* System Status Register */
+
+/* PSYSR Register Bits */
+#define PSYSR_AFF_L0		BIT(29)	/* Affinity Level 0 */
+
+/* V2M System Registers */
+#define V2M_SYS_CFGCTRL_OFF		0xa4	/* System Configuration Control Register */
+
+/* V2M Configuration Control Register bits */
+#define V2M_CFGCTRL_START		BIT(31)	/* Start operation */
+#define V2M_CFGCTRL_RW			BIT(30)	/* Read/Write operation */
+#define V2M_CFGCTRL_FUNC_MASK		GENMASK(27, 20)	/* Function field */
+#define V2M_CFGCTRL_FUNC(fn)		FIELD_PREP(V2M_CFGCTRL_FUNC_MASK, (fn))
+
+/* V2M System Configuration Functions */
+#define V2M_FUNC_REBOOT			0x09	/* System reboot */
+
+/*
+ * Memory mapping strategy:
+ *
+ * To conserve memory (especially page tables) in Zephyr, we use temporary
+ * mappings for hardware register access. Each operation maps the required
+ * registers, performs the operation, then unmaps them immediately.
+ *
+ * CPU power operations are infrequent and not performance-critical. Memory
+ * conservation is therefore more important than runtime optimizations.
+ */
+#define FVP_REGISTER_MAP_SIZE		0x1000	/* 4KB pages for register mapping */
+
+static inline void fvp_pwrc_write_pponr(uintptr_t pwrc_vaddr, unsigned long mpidr)
+{
+	sys_write32((uint32_t)mpidr, pwrc_vaddr + PWRC_PPONR_OFF);
+	LOG_DBG("FVP: PPONR write: MPIDR=0x%lx", mpidr);
+}
+
+static inline uint32_t fvp_pwrc_read_psysr(uintptr_t pwrc_vaddr, unsigned long mpidr)
+{
+	/* Write MPIDR to PSYSR to select which CPU to query */
+	sys_write32((uint32_t)mpidr, pwrc_vaddr + PWRC_PSYSR_OFF);
+
+	/* Read the status for the selected CPU */
+	return sys_read32(pwrc_vaddr + PWRC_PSYSR_OFF);
+}
+
+
+static int fvp_cpu_power_on(unsigned long target_mpidr, uintptr_t entry_point)
+{
+	uint8_t *pwrc_vaddr_ptr;
+	uintptr_t pwrc_vaddr;
+	uint32_t psysr;
+	int timeout = 10000; /* 1 second timeout */
+
+	LOG_DBG("FVP: Powering on CPU MPIDR=0x%lx, entry=0x%lx",
+		target_mpidr, entry_point);
+
+	/* Map power controller registers once for the entire operation */
+	k_mem_map_phys_bare(&pwrc_vaddr_ptr, FVP_PWRC_BASE, FVP_REGISTER_MAP_SIZE,
+			    K_MEM_PERM_RW | K_MEM_CACHE_NONE);
+	pwrc_vaddr = (uintptr_t)pwrc_vaddr_ptr;
+
+	/*
+	 * Wait for any pending power-off to complete.
+	 * The target CPU must be in OFF state before we can power it on.
+	 */
+	do {
+		psysr = fvp_pwrc_read_psysr(pwrc_vaddr, target_mpidr);
+		if (timeout-- <= 0) {
+			LOG_ERR("FVP: Timeout waiting for CPU 0x%lx power-off "
+				"to complete, PSYSR=0x%x", target_mpidr, psysr);
+			k_mem_unmap_phys_bare(pwrc_vaddr_ptr, FVP_REGISTER_MAP_SIZE);
+			return -ETIMEDOUT;
+		}
+		k_busy_wait(100);
+	} while ((psysr & PSYSR_AFF_L0) != 0);
+
+	LOG_DBG("FVP: CPU 0x%lx is powered off (PSYSR=0x%x)", target_mpidr, psysr);
+
+	/* Power on the target CPU via FVP power controller */
+	fvp_pwrc_write_pponr(pwrc_vaddr, target_mpidr);
+
+	/* Unmap power controller registers */
+	k_mem_unmap_phys_bare(pwrc_vaddr_ptr, FVP_REGISTER_MAP_SIZE);
+
+	/* Ensure power-on request completes */
+	barrier_dsync_fence_full();
+
+	/* Send event to wake up the target CPU from WFE loop */
+	__asm__ volatile("sev" ::: "memory");
+
+	LOG_DBG("FVP: Power-on request completed for CPU 0x%lx", target_mpidr);
+	return 0;
+}
+
+int pm_cpu_on(unsigned long mpidr, uintptr_t entry_point)
+{
+	return fvp_cpu_power_on(mpidr, entry_point);
+}
+
+int pm_cpu_off(void)
+{
+	/*
+	 * This is incompatible with our register mapping strategy.
+	 * A CPU that shuts itself down might not complete the register
+	 * unmapping before losing power.
+	 */
+	return -ENOTSUP;
+}
+
+static inline void fvp_v2m_sys_cfgwrite(uint32_t function)
+{
+	uint8_t *v2m_vaddr_ptr;
+	uintptr_t v2m_vaddr;
+	uint32_t val = V2M_CFGCTRL_START | V2M_CFGCTRL_RW | V2M_CFGCTRL_FUNC(function);
+
+	/* Temporarily map V2M system registers */
+	k_mem_map_phys_bare(&v2m_vaddr_ptr, FVP_V2M_SYSREGS_BASE, FVP_REGISTER_MAP_SIZE,
+			    K_MEM_PERM_RW | K_MEM_CACHE_NONE);
+	v2m_vaddr = (uintptr_t)v2m_vaddr_ptr;
+
+	sys_write32(val, v2m_vaddr + V2M_SYS_CFGCTRL_OFF);
+
+	LOG_DBG("FVP: V2M SYS_CFGCTRL write: 0x%x (func=0x%x)", val, function);
+
+	/* Unmap V2M registers */
+	k_mem_unmap_phys_bare(v2m_vaddr_ptr, FVP_REGISTER_MAP_SIZE);
+}
+
+int pm_system_reset(unsigned char reset_type)
+{
+	LOG_DBG("FVP: System reset requested (type=%u)", reset_type);
+
+	/*
+	 * FVP supports system reset via the V2M System Configuration Controller.
+	 * Both warm and cold reset use the same mechanism - the V2M reboot function.
+	 */
+	fvp_v2m_sys_cfgwrite(V2M_FUNC_REBOOT);
+
+	/*
+	 * The reset should happen immediately, but in case it doesn't work,
+	 * we'll wait a bit and return an error.
+	 */
+	k_busy_wait(1000000); /* Wait 1 second */
+
+	LOG_ERR("FVP: System reset failed - system did not reset");
+	return -ETIMEDOUT;
+}
diff --git a/dts/bindings/pm_cpu_ops/arm,fvp-pwrc.yaml b/dts/bindings/pm_cpu_ops/arm,fvp-pwrc.yaml
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  ARM Fixed Virtual Platform (FVP) Power Controller (PWRC)
+
+  The FVP PWRC provides CPU power management capabilities on ARM Fixed Virtual
+  Platform models. This hardware block is part of the Base_PowerController
+  component and controls CPU power states for bare-metal operation when PSCI
+  firmware is not available.
+
+  The PWRC registers include:
+  - PPOFFR (0x00): Power off processor request
+  - PPONR (0x04): Power on processor request
+  - PCOFFR (0x08): Power off cluster request
+  - PWKUPR (0x0c): Wakeup request control
+  - PSYSR (0x10): System power status register
+
+  For system reset operations, this controller requires access to the V2M
+  System Registers (vexpress-sysreg).
+
+  Reference:
+    - Fast Models FVP Reference Guide (ARM DUI 0966)
+    - ARM Trusted Firmware-A: drivers/arm/fvp/fvp_pwrc.c
+
+compatible: "arm,fvp-pwrc"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+    description: |
+      Base address and size of the FVP Power Controller register block.
+      Typically 0x1c100000 with size 0x1000 on FVP Base RevC platforms.
+
+  arm,vexpress-sysreg:
+    type: phandle
+    description: |
+      Reference to the ARM Versatile Express System Registers (v2m_sysreg) node.
+      Required for system reset operations via the SYS_CFGCTRL register.
+      See ARM Motherboard Express µATX Technical Reference Manual (DUI 0447).
