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nhutnguyenkckartben
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drivers: gpio: Add support for RZ/A3UL
Add GPIO driver support for RZ/A3UL Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
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9 files changed

+328
-52
lines changed

9 files changed

+328
-52
lines changed

‎boards/renesas/rza3ul_smarc/rza3ul_smarc.dts‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77

88
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
99
#include <zephyr/dt-bindings/input/input-event-codes.h>
10+
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1011
#include <freq.h>
1112
#include <arm64/renesas/rz/rza/r9a07g063.dtsi>
1213
#include "rza3ul_smarc-pinctrl.dtsi"

‎drivers/gpio/Kconfig.renesas_rz‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,10 @@ config GPIO_RENESAS_RZ
88
select USE_RZ_FSP_IOPORT
99
help
1010
Enable Renesas RZ series gpio driver.
11+
12+
config GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT
13+
bool
14+
default y
15+
depends on DT_HAS_RENESAS_RZ_GPIO_INT_ENABLED
16+
help
17+
GPIO pins can generate interrupts at port mode.

‎drivers/gpio/gpio_renesas_rz.c‎

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <zephyr/drivers/gpio/gpio_utils.h>
1616
#include "gpio_renesas_rz.h"
1717
#include <zephyr/logging/log.h>
18-
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
18+
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
1919
#include "r_icu.h"
2020
#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
2121
#endif
@@ -33,7 +33,7 @@ struct gpio_rz_config {
3333
const ioport_api_t *fsp_api;
3434
const struct device *int_dev;
3535
uint8_t int_num[GPIO_RZ_MAX_INT_NUM];
36-
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
36+
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
3737
const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM];
3838

3939
void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg);
@@ -45,7 +45,7 @@ struct gpio_rz_data {
4545
sys_slist_t cb;
4646
ioport_instance_ctrl_t *fsp_ctrl;
4747
struct k_spinlock lock;
48-
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
48+
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
4949
uint8_t pin[GPIO_RZ_MAX_INT_NUM];
5050
#endif
5151
};
@@ -287,18 +287,14 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
287287
return 0;
288288
}
289289

290-
#define GPIO_RZ_HAS_INTERRUPT \
291-
DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) | \
292-
DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_ext_irq)
293-
294-
#if GPIO_RZ_HAS_INTERRUPT
290+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
295291
static int gpio_rz_int_disable(const struct device *dev, const struct device *gpio_dev,
296292
uint8_t int_num, gpio_pin_t pin)
297293
{
298-
#if defined(CONFIG_SOC_SERIES_RZG3S)
299-
volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
300-
volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
301-
volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
294+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
295+
volatile uint32_t *tssr = &R_INTC->TSSR0;
296+
volatile uint32_t *titsr = &R_INTC->TITSR0;
297+
volatile uint32_t *tscr = &R_INTC->TSCR;
302298
struct gpio_rz_int_data *data = dev->data;
303299

304300
/* Get register offset base on interrupt number. */
@@ -319,14 +315,14 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
319315

320316
data->gpio_mapping[int_num].gpio_dev = NULL;
321317
data->gpio_mapping[int_num].pin = UINT8_MAX;
322-
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
318+
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
323319
const struct gpio_rz_config *gpio_config = gpio_dev->config;
324320
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
325321

326322
if (device_is_ready(eirq_dev)) {
327323
intc_rz_ext_irq_disable(eirq_dev);
328324
}
329-
#endif /* CONFIG_SOC_SERIES_* */
325+
#endif /* CONFIG_RENESAS_RZ_EXT_IRQ */
330326

331327
return 0;
332328
}
@@ -340,9 +336,9 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
340336

341337
const struct gpio_rz_config *gpio_config = gpio_dev->config;
342338

343-
#if defined(CONFIG_SOC_SERIES_RZG3S)
344-
volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
345-
volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
339+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
340+
volatile uint32_t *tssr = &R_INTC->TSSR0;
341+
volatile uint32_t *titsr = &R_INTC->TITSR0;
346342
struct gpio_rz_int_data *int_data = int_dev->data;
347343

348344
tssr = &tssr[int_num / 4];
@@ -356,12 +352,12 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
356352
if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
357353
int_data->irq_set_edge |= BIT(int_num);
358354
/* Clear interrupt status. */
359-
R_INTC_IM33->TSCR &= ~BIT(int_num);
355+
R_INTC->TSCR &= ~BIT(int_num);
360356
}
361357
irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
362358
int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
363359
int_data->gpio_mapping[int_num].pin = pin;
364-
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
360+
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
365361
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
366362
struct gpio_rz_data *gpio_data = gpio_dev->data;
367363

@@ -372,7 +368,7 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
372368
intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num],
373369
(void *)gpio_dev);
374370
}
375-
#endif /* CONFIG_SOC_SERIES_* */
371+
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
376372

377373
return 0;
378374
}
@@ -445,10 +441,10 @@ static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callbac
445441

446442
static void gpio_rz_isr(uint16_t irq, void *param)
447443
{
448-
#if defined(CONFIG_SOC_SERIES_RZG3S)
444+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
449445
const struct device *dev = param;
450446
struct gpio_rz_int_data *int_data = dev->data;
451-
volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
447+
volatile uint32_t *tscr = &R_INTC->TSCR;
452448

453449
if (!(*tscr & BIT(irq))) {
454450
LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
@@ -464,16 +460,16 @@ static void gpio_rz_isr(uint16_t irq, void *param)
464460
struct gpio_rz_data *gpio_data = gpio_dev->data;
465461

466462
gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
467-
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
463+
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
468464
const struct device *gpio_dev = (const struct device *)param;
469465
struct gpio_rz_data *gpio_data = gpio_dev->data;
470466
uint8_t pin = gpio_data->pin[irq];
471467

472468
gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
473-
#endif /* CONFIG_SOC_SERIES_* */
469+
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
474470
}
475471

476-
#endif /* GPIO_RZ_HAS_INTERRUPT */
472+
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
477473

478474
static DEVICE_API(gpio, gpio_rz_driver_api) = {
479475
.pin_configure = gpio_rz_pin_configure,
@@ -485,7 +481,7 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
485481
.port_set_bits_raw = gpio_rz_port_set_bits_raw,
486482
.port_clear_bits_raw = gpio_rz_port_clear_bits_raw,
487483
.port_toggle_bits = gpio_rz_port_toggle_bits,
488-
#if GPIO_RZ_HAS_INTERRUPT
484+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
489485
.pin_interrupt_configure = gpio_rz_pin_interrupt_configure,
490486
.manage_callback = gpio_rz_manage_callback,
491487
#endif
@@ -500,7 +496,8 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
500496

501497
#define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ())
502498

503-
#if defined(CONFIG_SOC_SERIES_RZG3S)
499+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
500+
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
504501

505502
#define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int))
506503

@@ -537,7 +534,7 @@ static int gpio_rz_int_init(const struct device *dev)
537534
UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
538535
DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
539536

540-
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) && GPIO_RZ_HAS_INTERRUPT
537+
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
541538

542539
GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
543540

@@ -558,9 +555,12 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
558555
#define GPIO_RZ_INT_DEFINE(inst) \
559556
.eirq_dev = {ALL_EIRQ_DEV_GET(inst)}, \
560557
.cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))}
558+
559+
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
560+
561561
#else
562562
#define GPIO_RZ_INT_DEFINE(inst)
563-
#endif /* CONFIG_SOC_SERIES_* */
563+
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
564564

565565
#define VALUE_2X(i, _) UTIL_X2(i)
566566
#define PIN_IRQ_GET(idx, inst) \
@@ -573,7 +573,7 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
573573
FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst, \
574574
LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
575575

576-
#define RZG_GPIO_PORT_INIT(inst) \
576+
#define RZ_GPIO_PORT_INIT(inst) \
577577
static ioport_cfg_t g_ioport_##inst##_cfg = { \
578578
.number_of_pins = 0, \
579579
.p_pin_cfg_data = NULL, \
@@ -599,4 +599,4 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
599599
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config, \
600600
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api);
601601

602-
DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT)
602+
DT_INST_FOREACH_STATUS_OKAY(RZ_GPIO_PORT_INIT)

‎drivers/gpio/gpio_renesas_rz.h‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,12 +11,22 @@
1111

1212
#define GPIO_RZ_INT_UNSUPPORTED 0xF
1313

14-
#if defined(CONFIG_SOC_SERIES_RZG3S)
14+
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)
1515
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1616

17+
#if defined(CONFIG_SOC_SERIES_RZG3S)
1718
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
1819
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
1920
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
21+
#define GPIO_RZ_TINT_IRQ_OFFSET 429
22+
#define R_INTC R_INTC_IM33
23+
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
24+
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P10)
25+
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM10)
26+
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10)
27+
#define GPIO_RZ_TINT_IRQ_OFFSET 476
28+
#define R_INTC R_INTC_IA55
29+
#endif
2030

2131
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port + (pin / 4)])
2232
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port + (pin / 4)])
@@ -33,7 +43,6 @@
3343
#define GPIO_RZ_MAX_PORT_NUM 19
3444
#define GPIO_RZ_MAX_INT_NUM 32
3545

36-
#define GPIO_RZ_TINT_IRQ_OFFSET 429
3746
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
3847

3948
#define GPIO_RZ_INT_EDGE_RISING 0x0
@@ -46,8 +55,8 @@
4655
#define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8)
4756
#define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2)
4857

49-
#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
50-
#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U)
58+
#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
59+
#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U)
5160

5261
#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE
5362
#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE))

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