soc: imxrt: Clean up INIT_ARM_PLL config

Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.

The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.

And of course, code for this was a mess, clean up a bit.

Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.

Signed-off-by: Declan Snyder <[email protected]>

Author: decsny

soc/nxp/imxrt/Kconfig

@@ -179,6 +179,9 @@ config DCDC_VALUE
 	hex "DCDC value for VDD_SOC"
 
 config INIT_ARM_PLL
+	default y
+	depends on !SOC_MIMXRT1011 && !SOC_MIMXRT1015 && \
+		   !SOC_MIMXRT1021 && !SOC_MIMXRT1024
 	bool "Initialize ARM PLL"
 
 config INIT_VIDEO_PLL

soc/nxp/imxrt/imxrt10xx/Kconfig

@@ -65,7 +65,6 @@ config SOC_MIMXRT1042
 	select HAS_MCUX_SEMC
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
-	select INIT_ARM_PLL
 	select INIT_SYS_PLL
 
 config SOC_MIMXRT1052
@@ -74,7 +73,6 @@ config SOC_MIMXRT1052
 	select HAS_MCUX_SEMC
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
-	select INIT_ARM_PLL
 	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
 	select HAS_MCUX_USDHC1
 	select HAS_MCUX_USDHC2
@@ -91,7 +89,6 @@ config SOC_MIMXRT1062
 	select HAS_MCUX_SNVS
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
-	select INIT_ARM_PLL
 	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
 	select HAS_MCUX_USDHC1
 	select HAS_MCUX_USDHC2
@@ -110,7 +107,6 @@ config SOC_MIMXRT1064
 	select HAS_MCUX_SRC
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
-	select INIT_ARM_PLL
 	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
 	select HAS_MCUX_USDHC1
 	select HAS_MCUX_USDHC2

soc/nxp/imxrt/imxrt10xx/soc.c

@@ -33,13 +33,6 @@
 		     DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \
 		     #podf " is out of supported range (" #a ", " #b ")")
 
-#ifdef CONFIG_INIT_ARM_PLL
-/* ARM PLL configuration for RUN mode */
-const clock_arm_pll_config_t armPllConfig = {
-	.loopDivider = 100U
-};
-#endif
-
 #if CONFIG_INIT_SYS_PLL
 /* Configure System PLL */
 const clock_sys_pll_config_t sysPllConfig = {
@@ -132,6 +125,10 @@ __weak void clock_init(void)
 #endif
 
 #ifdef CONFIG_INIT_ARM_PLL
+	/* ARM PLL configuration for RUN mode */
+	static const clock_arm_pll_config_t armPllConfig = {
+		.loopDivider = 100U
+	};
 	CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
 #endif
 

soc/nxp/imxrt/imxrt118x/Kconfig

@@ -14,7 +14,6 @@ config SOC_SERIES_IMXRT118X
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select ARM_MPU
-	select INIT_ARM_PLL
 	select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE

soc/nxp/imxrt/imxrt11xx/Kconfig

@@ -23,7 +23,6 @@ config SOC_SERIES_IMXRT11XX
 	select HAS_MCUX_FLEXSPI
 	select HAS_MCUX_FLEXCAN
 	select CPU_HAS_ARM_MPU
-	select INIT_ARM_PLL
 	select INIT_VIDEO_PLL
 	select HAS_MCUX_EDMA
 	select CPU_HAS_ICACHE if CPU_CORTEX_M7

soc/nxp/imxrt/imxrt11xx/soc.c

@@ -56,31 +56,6 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
 #endif
 
-#ifdef CONFIG_INIT_ARM_PLL
-
-#if defined(CONFIG_SOC_MIMXRT1176)
-#define DEFAULT_LOOPDIV 83
-#define DEFAULT_POSTDIV 2
-#elif defined(CONFIG_SOC_MIMXRT1166)
-#define DEFAULT_LOOPDIV 100
-#define DEFAULT_POSTDIV 4
-#else
-/*
- * Check that the ARM PLL has a multiplier and divider set
- */
-BUILD_ASSERT(DT_NODE_HAS_PROP(DT_NODELABEL(arm_pll), clock_mult),
-	     "ARM PLL must have clock-mult property");
-BUILD_ASSERT(DT_NODE_HAS_PROP(DT_NODELABEL(arm_pll), clock_div),
-	     "ARM PLL must have clock-div property");
-#endif
-
-static const clock_arm_pll_config_t armPllConfig = {
-	.postDivider = CONCAT(kCLOCK_PllPostDiv,
-			      DT_PROP_OR(DT_NODELABEL(arm_pll), clock_div, DEFAULT_POSTDIV)),
-	.loopDivider = DT_PROP_OR(DT_NODELABEL(arm_pll), clock_mult, DEFAULT_LOOPDIV) * 2,
-};
-#endif
-
 static const clock_sys_pll2_config_t sysPll2Config = {
 	/* Denominator of spread spectrum */
 	.mfd = 268435455,
@@ -250,10 +225,15 @@ __weak void clock_init(void)
 	 * changed in the following PLL/PFD configuration code.
 	 */
 
-#ifdef CONFIG_INIT_ARM_PLL
-	/* Init Arm Pll. */
-	CLOCK_InitArmPll(&armPllConfig);
-#endif
+
+	static const clock_arm_pll_config_t armPllConfig = {
+		.postDivider = CONCAT(kCLOCK_PllPostDiv, DT_PROP(DT_NODELABEL(arm_pll), clock_div)),
+		.loopDivider = DT_PROP(DT_NODELABEL(arm_pll), clock_mult) * 2,
+	};
+
+	if (IS_ENABLED(CONFIG_INIT_ARM_PLL)) {
+		CLOCK_InitArmPll(&armPllConfig);
+	}
 
 	if (IS_ENABLED(CONFIG_ETH_NXP_ENET)) {
 		/* For default clocking, we will only use pll1 for div2 output for enet */