drivers: mbox: Add mailbox driver for SOPHGO CVI series

This implements a mailbox driver for CV18xx, a series of multi-core SoCs by
SOPHGO.

This driver enables the little core of CV18xx running RTOS to communicate
with its big core running Linux.

Signed-off-by: honglin leng <[email protected]>
Signed-off-by: Chen Xingyu <[email protected]>

Author: lenghonglin

drivers/mbox/CMakeLists.txt

@@ -22,3 +22,4 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_IVSHMEM mbox_ivshmem.c)
 zephyr_library_sources_ifdef(CONFIG_MBOX_TI_OMAP_MAILBOX   mbox_ti_omap.c)
 zephyr_library_sources_ifdef(CONFIG_MBOX_RENESAS_RZ_MHU mbox_renesas_rz_mhu.c)
 zephyr_library_sources_ifdef(CONFIG_MBOX_MHUV3   mbox_mhuv3.c)
+zephyr_library_sources_ifdef(CONFIG_MBOX_SOPHGO_CVI mbox_sophgo_cvi.c)

drivers/mbox/Kconfig

@@ -26,6 +26,7 @@ source "drivers/mbox/Kconfig.ivshmem"
 source "drivers/mbox/Kconfig.ti_omap"
 source "drivers/mbox/Kconfig.renesas_rz"
 source "drivers/mbox/Kconfig.mhuv3"
+source "drivers/mbox/Kconfig.sophgo"
 
 
 config MBOX_INIT_PRIORITY

drivers/mbox/Kconfig.sophgo

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 honglin leng <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config MBOX_SOPHGO_CVI
+	bool "SOPHGO CVI series Mailbox controller"
+	default y
+	depends on DT_HAS_SOPHGO_CVI_MAILBOX_ENABLED
+	help
+	  Enable driver for the SOPHGO CVI series Mailbox.

drivers/mbox/mbox_sophgo_cvi.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2024 honglin leng <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/irq.h>
+#include <string.h>
+
+#define DT_DRV_COMPAT sophgo_cvi_mailbox
+
+#define MBOX_BASE   DT_INST_REG_ADDR(0)
+#define MBOX_TX_CPU DT_INST_PROP(0, tx_cpu)
+#define MBOX_RX_CPU DT_INST_PROP(0, rx_cpu)
+
+#define MBOX_INT_ENABLE(cpu) (MBOX_BASE + 0x00 + (0x04 * cpu))
+#define MBOX_INT_CLEAR(cpu)  (MBOX_BASE + 0x10 + (0x10 * cpu))
+#define MBOX_INT_DONE(cpu)   (MBOX_BASE + 0x18 + (0x10 * cpu))
+#define MBOX_INT_TRIGER      (MBOX_BASE + 0x60)
+#define MBOX_BUFFER          (MBOX_BASE + 0x400)
+
+#define MBOX_MAX_NUM 8
+
+struct mbox_cvi_data {
+	mbox_callback_t cb[MBOX_MAX_NUM];
+	void *user_data[MBOX_MAX_NUM];
+};
+
+static struct mbox_cvi_data mbox_data;
+
+static void mbox_isr(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	uint8_t set_val;
+	uint8_t valid_val;
+	uint8_t tmp_valid_val;
+	struct mbox_msg msg;
+
+	set_val = sys_read8(MBOX_INT_DONE(MBOX_RX_CPU));
+	if (set_val) {
+		for (int i = 0; i < MBOX_MAX_NUM; i++) {
+			valid_val = set_val & BIT(i);
+			if (valid_val) {
+				msg.data = (const unsigned long *)MBOX_BUFFER + i;
+				sys_write8(valid_val, MBOX_INT_CLEAR(MBOX_RX_CPU));
+				tmp_valid_val = sys_read8(MBOX_INT_ENABLE(MBOX_RX_CPU));
+				tmp_valid_val &= ~valid_val;
+				sys_write8(tmp_valid_val, MBOX_INT_ENABLE(MBOX_RX_CPU));
+				if (mbox_data.cb[i] != NULL) {
+					mbox_data.cb[i](dev, i, mbox_data.user_data[i], &msg);
+					*(unsigned long *)msg.data = 0x0;
+				}
+			}
+		}
+	}
+}
+
+static int mbox_cvi_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg)
+{
+	uint8_t tmp_mbox_info;
+
+	ARG_UNUSED(dev);
+
+	memcpy((unsigned long *)MBOX_BUFFER + channel, msg->data, msg->size);
+	sys_write8(BIT(channel), MBOX_INT_CLEAR(MBOX_TX_CPU));
+	tmp_mbox_info = sys_read8(MBOX_INT_ENABLE(MBOX_TX_CPU));
+	tmp_mbox_info |= BIT(channel);
+	sys_write8(tmp_mbox_info, MBOX_INT_ENABLE(MBOX_TX_CPU));
+	sys_write8(BIT(channel), MBOX_INT_TRIGER);
+
+	return 0;
+}
+
+static int mbox_cvi_register_callback(const struct device *dev, uint32_t channel,
+				      mbox_callback_t cb, void *user_data)
+{
+	ARG_UNUSED(dev);
+
+	if (channel >= MBOX_MAX_NUM) {
+		return -EINVAL;
+	}
+
+	mbox_data.cb[channel] = cb;
+	mbox_data.user_data[channel] = user_data;
+
+	return 0;
+}
+
+static int mbox_cvi_mtu_get(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* We only support signalling */
+	return 0;
+}
+
+static uint32_t mbox_cvi_max_channels_get(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return MBOX_MAX_NUM;
+}
+
+static int mbox_cvi_set_enabled(const struct device *dev, uint32_t channel, bool enable)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(channel);
+	ARG_UNUSED(enable);
+
+	return 0;
+}
+
+static int mbox_cvi_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), mbox_isr, DEVICE_DT_INST_GET(0), 0);
+	irq_enable(DT_INST_IRQN(0));
+
+	return 0;
+}
+
+static DEVICE_API(mbox, mbox_cvi_driver_api) = {
+	.send = mbox_cvi_send,
+	.register_callback = mbox_cvi_register_callback,
+	.mtu_get = mbox_cvi_mtu_get,
+	.max_channels_get = mbox_cvi_max_channels_get,
+	.set_enabled = mbox_cvi_set_enabled,
+};
+
+DEVICE_DT_INST_DEFINE(0, mbox_cvi_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY,
+		      &mbox_cvi_driver_api);

dts/bindings/mbox/sophgo,cvi-mailbox.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) 2024 honglin leng <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SOPHGO CVI series Mailbox controller
+
+compatible: "sophgo,cvi-mailbox"
+
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  channel-max:
+    type: int
+    required: true
+    description: Supported channels max
+
+  rx-cpu:
+    type: int
+    enum: [1, 2, 3, 4]
+    description: |
+      Receiver CPU Index.
+
+  tx-cpu:
+    type: int
+    enum: [1, 2, 3, 4]
+    description: |
+      Sender CPU Index.The CVI platform has a total of 4 CPUs, each with its own
+      mailbox.
+
+      The mailbox controller can be used to send messages between CPUs.
+
+mbox-cells:
+  - channel

dts/riscv/sophgo/cv180x.dtsi

@@ -13,6 +13,17 @@
 	soc {
 		compatible = "sophgo,cv180x", "simple-bus";
 
+		mbox: mailbox@1900000 {
+			compatible = "sophgo,cvi-mailbox";
+			reg = <0x1900000 DT_SIZE_K(4)>;
+			interrupts = <61 1>;
+			channel-max = <8>;
+			tx-cpu = <1>;
+			rx-cpu = <2>;
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@3001000 {
 			compatible = "sophgo,cvi-pinctrl";
 			reg = <0x3001000 DT_SIZE_K(4)>;

dts/riscv/sophgo/cv181x.dtsi

@@ -13,6 +13,17 @@
 	soc {
 		compatible = "sophgo,cv181x", "simple-bus";
 
+		mbox: mailbox@1900000 {
+			compatible = "sophgo,cvi-mailbox";
+			reg = <0x1900000 DT_SIZE_K(4)>;
+			interrupts = <61 1>;
+			channel-max = <8>;
+			tx-cpu = <1>;
+			rx-cpu = <2>;
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@3001000 {
 			compatible = "sophgo,cvi-pinctrl";
 			reg = <0x3001000 DT_SIZE_K(4)>;