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congnguyenhuucongnguyenhuu
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drivers: memc_nxp_s32_qspi: add support for s32ze
Add support QSPI secure flash protection (SFP) Signed-off-by: Cong Nguyen Huu <[email protected]>
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‎drivers/memc/memc_nxp_s32_qspi.c‎

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@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(nxp_s32_qspi_memc, CONFIG_MEMC_LOG_LEVEL);
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
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#include <soc.h>
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#include "memc_nxp_s32_qspi.h"
@@ -154,6 +155,81 @@ uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev)
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QSPI_PORT_SIZE(n, side_upper) \
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.readMode##side_upper = QSPI_READ_MODE(n, side, side_upper),
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#if FEATURE_QSPI_HAS_SFP
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#if QSPI_IP_SFP_ENABLE_MDAD
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#define SFP_MDAD_NODE(n) DT_INST_CHILD(n, sfp_mdad)
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#define QSPI_SECURE_ATTRIBUTE(node_id) \
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(DT_PROP(node_id, secure_attribute) == NXP_S32_QSPI_NON_SECURE ? QSPI_IP_SFP_UNSECURE : \
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(DT_PROP(node_id, secure_attribute) == NXP_S32_QSPI_SECURE ? QSPI_IP_SFP_SECURE : \
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(DT_PROP(node_id, secure_attribute) == (NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE) ?\
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QSPI_IP_SFP_BOTH : \
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QSPI_IP_SFP_RESERVED)))
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#define _QSPI_SFP_MDAD_CFG(node_id, n) \
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{ \
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.SecureAttribute = QSPI_SECURE_ATTRIBUTE(node_id), \
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.MaskType = DT_ENUM_IDX(node_id, mask_type), \
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.Valid = true, \
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.Mask = DT_PROP(node_id, mask), \
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.DomainId = DT_PROP(node_id, domain_id), \
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},
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#define QSPI_SFP_MDAD_CFG(n) \
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.Tg = { \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_MDAD_NODE(n), _QSPI_SFP_MDAD_CFG, n)\
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},
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#endif /* QSPI_IP_SFP_ENABLE_MDAD */
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#if QSPI_IP_SFP_ENABLE_FRAD
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#define SFP_FRAD_NODE(n) DT_INST_CHILD(n, sfp_frad)
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#define QSPI_ACP_POLICY(node_id) \
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(DT_PROP(node_id, master_domain_acp_policy) == NXP_S32_QSPI_SECURE ? \
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QSPI_IP_SFP_ACP_SECURE :\
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(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_NON_SECURE | \
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NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_PRIVILEGED : \
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(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_SECURE | \
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NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_SECURE_PRIVILEGED :\
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(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_NON_SECURE | \
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NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_ALL : \
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QSPI_IP_SFP_ACP_NONE))))
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#define QSPI_EXCLUSIVE_ACCESS_LOCK(node_id) \
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(DT_ENUM_IDX(node_id, exclusive_access_lock) == 0 ? QSPI_IP_SFP_EAL_DISABLED : \
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(DT_ENUM_IDX(node_id, exclusive_access_lock) == 1 ? QSPI_IP_SFP_EAL_OWNER : \
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QSPI_IP_SFP_EAL_NONE))
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#define _QSPI_SFP_FRAD_CFG(node_id, n) \
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{ \
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.StartAddress = DT_REG_ADDR(node_id), \
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.EndAddress = DT_REG_ADDR(node_id) + DT_REG_SIZE(node_id) - 1, \
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.Valid = true, \
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.Md0Acp = QSPI_ACP_POLICY(node_id), \
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.Md1Acp = QSPI_ACP_POLICY(node_id), \
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.ExclusiveAccessLock = QSPI_EXCLUSIVE_ACCESS_LOCK(node_id), \
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.ExclusiveAccessOwner = DT_PROP(node_id, exclusive_access_owner), \
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},
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#define QSPI_SFP_FRAD_CFG(n) \
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.Frad = { \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_FRAD_NODE(n), _QSPI_SFP_FRAD_CFG, n)\
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},
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#endif /* QSPI_IP_SFP_ENABLE_FRAD */
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#define QSPI_SFP_MASTER_TIMEOUT_CYCLES 0xffff
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#define QSPI_SFP_CFG(n) \
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IF_ENABLED(QSPI_IP_SFP_ENABLE_GLOBAL, \
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(.SfpCfg = { \
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.MasterTimeout = QSPI_SFP_MASTER_TIMEOUT_CYCLES, \
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IF_ENABLED(QSPI_IP_SFP_ENABLE_MDAD, (QSPI_SFP_MDAD_CFG(n))) \
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IF_ENABLED(QSPI_IP_SFP_ENABLE_FRAD, (QSPI_SFP_FRAD_CFG(n))) \
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},))
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#endif /* FEATURE_QSPI_HAS_SFP */
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#define MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n) \
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BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_masters) == QSPI_IP_AHB_BUFFERS, \
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"ahb-buffers-masters must be of size QSPI_IP_AHB_BUFFERS"); \
@@ -174,6 +250,7 @@ uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev)
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QSPI_DATA_CFG(n) \
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QSPI_ADDR_CFG(n) \
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QSPI_BYTES_SWAP_ADDR(n) \
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IF_ENABLED(FEATURE_QSPI_HAS_SFP, (QSPI_SFP_CFG(n))) \
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}
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#define MEMC_NXP_S32_QSPI_INIT_DEVICE(n) \

‎dts/bindings/qspi/nxp,s32-qspi-sfp-frad.yaml‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP S32 Quad Serial Peripheral Interface (QSPI) Secure Flash Protection SFP FRAD.
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The SFP FRAD performs second-level checks on input flash write and erase transactions,
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based on the address range of each transaction.
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compatible: "nxp,s32-qspi-sfp-frad"
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child-binding:
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properties:
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reg:
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type: array
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required: true
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master-domain-acp-policy:
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type: int
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required: true
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description: |
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Selects the master domain access control policy, defined in dt-bindings/qspi/nxp-s32-qspi.h:
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- NXP_S32_QSPI_NON_SECURE: Selects the non-secure access control policy.
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- NXP_S32_QSPI_SECURE: Selects the secure access control policy.
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- NXP_S32_QSPI_PRIVILEGE: Selects the privilege access control policy.
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Allowed combinations:
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- NXP_S32_QSPI_SECURE
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- NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE
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- NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_PRIVILEGE
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- NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE
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exclusive-access-lock:
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type: string
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enum:
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- DISABLED
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- OWNER
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- NONE
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default: DISABLED
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description: |
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Selects the exclusive access lock:
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- DISABLED: The exclusive access lock disabled, granting write permissions for all masters
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- ENABLED: The exclusive access lock enabled, granting write permissions only to the
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exclusive access owner master and disabling write permissions for other masters.
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- NONE: This configuration should not be used
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The default corresponds to the reset value of the register field.
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exclusive-access-owner:
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type: int
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default: 0
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description: |
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The domain master ID that owns the exclusive access lock.
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Valid range: 0 - 63. The default corresponds to the reset
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value of the register field.

‎dts/bindings/qspi/nxp,s32-qspi-sfp-mdad.yaml‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP S32 Quad Serial Peripheral Interface (QSPI) Secure Flash Protection SFP MDAD.
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The SFP MDAD performs first-level checks on input transactions, based on the secure attribute
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and MGID associated with each transaction.
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compatible: "nxp,s32-qspi-sfp-mdad"
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child-binding:
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properties:
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secure-attribute:
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type: int
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required: true
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description: |
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Selects the secure attribute, defined in dt-bindings/qspi/nxp-s32-qspi.h:
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- NXP_S32_QSPI_NON_SECURE: Allow the bus attribute for this master to non-secure
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- NXP_S32_QSPI_SECURE: Allow the bus attribute for this master to secure
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Allowed combinations:
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- NXP_S32_QSPI_NON_SECURE
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- NXP_S32_QSPI_SECURE
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- NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE
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mask-type:
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type: string
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enum:
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- AND
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- OR
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default: AND
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description: |
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Selects the mask type:
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- AND: AND-ed mask
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- OR: OR-ed mask
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The default corresponds to the reset value of the register field.
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mask:
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type: int
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default: 0
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description: |
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Defines the mask value for the ID-Match comparison.
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Valid range: 0 - 63. The default corresponds to the
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reset value of the register field.
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domain-id:
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type: int
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required: true
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description: |
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Domain ID Reference value of the Domain-ID (MID) for MID-comparison.
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Valid range: 0 - 63.

‎include/zephyr/dt-bindings/qspi/nxp-s32-qspi.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
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#include <zephyr/dt-bindings/dt-util.h>
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/* The QSPI secure attribute and secure policy references */
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#define NXP_S32_QSPI_NON_SECURE BIT(0)
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#define NXP_S32_QSPI_SECURE BIT(1)
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#define NXP_S32_QSPI_PRIVILEGE BIT(2)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_ */

‎west.yml‎

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@@ -203,7 +203,7 @@ manifest:
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groups:
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- hal
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- name: hal_nxp
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revision: a7dc61f89063c1008f24ee21575c68d0165de91b
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revision: 5576d444d203e8973f7e8f5be18263b3d8a7bb1f
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path: modules/hal/nxp
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groups:
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- hal

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