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soburifabiobaltieri
soburi
authored and
fabiobaltieri
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dts: arm: renesas: ra4: Use renesas,ra-cgc-pclkblock driver
Switch the clock controller driver to renesas,ra-cgc-pclkblock which can be used with FSP. Signed-off-by: TOKITA Hiroshi <[email protected]>
1 parent 397c48a commit 183273e

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4 files changed

+88
-38
lines changed

4 files changed

+88
-38
lines changed

‎drivers/serial/uart_renesas_ra.c‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
#include <zephyr/drivers/uart.h>
1010
#include <zephyr/drivers/clock_control.h>
11+
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
1112
#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
1213
#include <zephyr/drivers/pinctrl.h>
1314
#include <zephyr/irq.h>
@@ -27,7 +28,7 @@ enum {
2728
struct uart_ra_cfg {
2829
mem_addr_t regs;
2930
const struct device *clock_dev;
30-
clock_control_subsys_t clock_id;
31+
const struct clock_control_ra_subsys_cfg clock_id;
3132
const struct pinctrl_dev_config *pcfg;
3233
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
3334
int (*irq_config_func)(const struct device *dev);
@@ -389,12 +390,13 @@ static int uart_ra_init(const struct device *dev)
389390
return -ENODEV;
390391
}
391392

392-
ret = clock_control_on(config->clock_dev, config->clock_id);
393+
ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id);
393394
if (ret < 0) {
394395
return ret;
395396
}
396397

397-
ret = clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_rate);
398+
ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_id,
399+
&data->clk_rate);
398400
if (ret < 0) {
399401
return ret;
400402
}
@@ -659,12 +661,13 @@ static const struct uart_driver_api uart_ra_driver_api = {
659661
.regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
660662
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
661663
.clock_id = \
662-
(clock_control_subsys_t)DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, id), \
664+
{ \
665+
.mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \
666+
.stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \
667+
}, \
663668
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
664-
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \
665-
.irq_config_func = irq_config_func_##n, \
666-
)) \
667-
}
669+
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
670+
(.irq_config_func = irq_config_func_##n,))}
668671

669672
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
670673

‎dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,4 @@
88
#define RA_SOC_HAS_MSTPCRE 1
99
#define RA_SOC_MSTPD5_CHANNELS 1
1010

11-
#include <zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h>
1211
#include <renesas/ra/ra4-cm4-common.dtsi>

‎dts/arm/renesas/ra/ra-cm4-common.dtsi‎

Lines changed: 76 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#include <freq.h>
99
#include <arm/armv7-m.dtsi>
1010
#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11+
#include <zephyr/dt-bindings/clock/ra_clock.h>
1112

1213
/ {
1314
cpus {
@@ -21,49 +22,51 @@
2122
};
2223
};
2324

24-
clocks {
25-
mosc: mosc {
26-
compatible = "fixed-clock";
25+
clocks: clocks {
26+
xtal: clock-main-osc {
27+
compatible = "renesas,ra-cgc-external-clock";
2728
clock-frequency = <1200000>;
2829
status = "disabled";
2930
#clock-cells = <0>;
3031
};
3132

32-
sosc: sosc {
33-
compatible = "fixed-clock";
33+
subclk: clock-subclk {
34+
compatible = "renesas,ra-cgc-subclk";
3435
clock-frequency = <32768>;
3536
status = "disabled";
3637
#clock-cells = <0>;
3738
};
3839

39-
hoco: hoco {
40+
hoco: clock-hoco {
4041
compatible = "fixed-clock";
4142
clock-frequency = <24000000>;
4243
status = "okay";
4344
#clock-cells = <0>;
4445
};
4546

46-
moco: moco {
47+
moco: clock-moco {
4748
compatible = "fixed-clock";
4849
clock-frequency = <8000000>;
4950
status = "okay";
5051
#clock-cells = <0>;
5152
};
5253

53-
loco: loco {
54+
loco: clock-loco {
5455
compatible = "fixed-clock";
5556
clock-frequency = <32768>;
5657
status = "okay";
5758
#clock-cells = <0>;
5859
};
5960

6061
pll: pll {
61-
compatible = "fixed-factor-clock";
62-
status = "disabled";
63-
clocks = <&mosc>;
64-
clock-div = <2>;
65-
clock-mult = <8>;
62+
compatible = "renesas,ra-cgc-pll";
6663
#clock-cells = <0>;
64+
65+
/* PLL */
66+
clocks = <&xtal>;
67+
div = <2>;
68+
mul = <8 0>;
69+
status = "disabled";
6770
};
6871
};
6972

@@ -82,19 +85,64 @@
8285
#interrupt-cells = <3>;
8386
};
8487

85-
cgc: cgc@4001e000 {
86-
compatible = "renesas,ra-clock-generation-circuit";
87-
reg = <0x4001e000 0x40 0x40047000 0x10>;
88-
reg-names = "system", "mstp";
89-
#clock-cells = <1>;
88+
pclkblock: pclkblock@4001e01c {
89+
compatible = "renesas,ra-cgc-pclk-block";
90+
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
91+
<0x40047008 4>;
92+
reg-names = "MSTPA", "MSTPB","MSTPC",
93+
"MSTPD";
94+
compatible = "renesas,ra-cgc-pclk-block";
95+
#clock-cells = <0>;
96+
clocks = <&moco>;
97+
status = "okay";
98+
99+
iclk: iclk {
100+
compatible = "renesas,ra-cgc-pclk";
101+
div = <16>;
102+
#clock-cells = <2>;
103+
status = "okay";
104+
};
105+
106+
pclka: pclka {
107+
compatible = "renesas,ra-cgc-pclk";
108+
div = <16>;
109+
#clock-cells = <2>;
110+
status = "okay";
111+
};
112+
113+
pclkb: pclkb {
114+
compatible = "renesas,ra-cgc-pclk";
115+
div = <16>;
116+
#clock-cells = <2>;
117+
status = "okay";
118+
};
90119

91-
clock-source = <&moco>;
92-
iclk-div = <16>;
93-
pclka-div = <16>;
94-
pclkb-div = <16>;
95-
pclkc-div = <16>;
96-
pclkd-div = <16>;
97-
fclk-div = <16>;
120+
pclkc: pclkc {
121+
compatible = "renesas,ra-cgc-pclk";
122+
div = <1>;
123+
#clock-cells = <2>;
124+
status = "okay";
125+
};
126+
127+
pclkd: pclkd {
128+
compatible = "renesas,ra-cgc-pclk";
129+
div = <16>;
130+
#clock-cells = <2>;
131+
status = "okay";
132+
};
133+
134+
fclk: fclk {
135+
compatible = "renesas,ra-cgc-pclk";
136+
div = <16>;
137+
#clock-cells = <2>;
138+
status = "okay";
139+
};
140+
141+
clkout: clkout {
142+
compatible = "renesas,ra-cgc-pclk";
143+
#clock-cells = <2>;
144+
status = "disabled";
145+
};
98146
};
99147

100148
fcu: flash-controller@4001c000 {
@@ -256,7 +304,7 @@
256304
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_AM>,
257305
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI_OR_ERI>;
258306
interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri";
259-
clocks = <&cgc RA_CLOCK_SCI(0)>;
307+
clocks = <&pclka MSTPB 31>;
260308
#clock-cells = <1>;
261309
status = "disabled";
262310
uart {
@@ -274,7 +322,7 @@
274322
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_ERI>,
275323
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_AM>;
276324
interrupt-names = "rxi", "txi", "tei", "eri", "am";
277-
clocks = <&cgc RA_CLOCK_SCI(1)>;
325+
clocks = <&pclka MSTPB 30>;
278326
#clock-cells = <1>;
279327
status = "disabled";
280328
uart {
@@ -292,7 +340,7 @@
292340
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_ERI>,
293341
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_AM>;
294342
interrupt-names = "rxi", "txi", "tei", "eri", "am";
295-
clocks = <&cgc RA_CLOCK_SCI(9)>;
343+
clocks = <&pclka MSTPB 22>;
296344
#clock-cells = <1>;
297345
status = "disabled";
298346
uart {

‎dts/arm/renesas/ra/ra4-cm4-common.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_ERI>,
5454
<RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_AM>;
5555
interrupt-names = "rxi", "txi", "tei", "eri", "am";
56-
clocks = <&cgc RA_CLOCK_SCI(2)>;
56+
clocks = <&pclka MSTPB 29>;
5757
#clock-cells = <1>;
5858
status = "disabled";
5959
uart {

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