@@ -124,7 +124,6 @@ static void set_interrupt_enabled(bool setting)
124124{
125125 volatile u32_t * intr_enable_reg = (u32_t * )TIMG_INT_ENA_TIMERS_REG (1 );
126126
127- wdt_esp32_unseal ();
128127 if (setting ) {
129128 * intr_enable_reg |= TIMG_WDT_INT_ENA ;
130129
@@ -135,7 +134,6 @@ static void set_interrupt_enabled(bool setting)
135134 * intr_enable_reg &= ~TIMG_WDT_INT_ENA ;
136135 irq_disable (CONFIG_WDT_ESP32_IRQ );
137136 }
138- wdt_esp32_seal ();
139137}
140138
141139static int wdt_esp32_set_config (struct device * dev , struct wdt_config * config )
@@ -160,29 +158,27 @@ static int wdt_esp32_set_config(struct device *dev, struct wdt_config *config)
160158
161159 if (config -> mode == WDT_MODE_RESET ) {
162160 /* Warm reset on timeout */
163- v |= TIMG_WDT_STG_SEL_RESET_CPU <<TIMG_WDT_STG0_S ;
161+ v |= TIMG_WDT_STG_SEL_RESET_SYSTEM <<TIMG_WDT_STG0_S ;
164162 v |= TIMG_WDT_STG_SEL_OFF <<TIMG_WDT_STG1_S ;
165163
166164 /* Disable interrupts for this mode. */
167- v &= ~TIMG_WDT_LEVEL_INT_EN ;
168-
169- set_interrupt_enabled (false);
165+ v &= ~(TIMG_WDT_LEVEL_INT_EN | TIMG_WDT_EDGE_INT_EN );
170166 } else if (config -> mode == WDT_MODE_INTERRUPT_RESET ) {
171167 /* Interrupt first, and warm reset if not reloaded */
172168 v |= TIMG_WDT_STG_SEL_INT <<TIMG_WDT_STG0_S ;
173- v |= TIMG_WDT_STG_SEL_RESET_CPU <<TIMG_WDT_STG1_S ;
169+ v |= TIMG_WDT_STG_SEL_RESET_SYSTEM <<TIMG_WDT_STG1_S ;
174170
175171 /* Use level-triggered interrupts. */
176172 v |= TIMG_WDT_LEVEL_INT_EN ;
177-
178- set_interrupt_enabled (true);
173+ v &= ~TIMG_WDT_EDGE_INT_EN ;
179174 } else {
180175 return - EINVAL ;
181176 }
182177
183178 wdt_esp32_unseal ();
184179 * reg = v ;
185180 adjust_timeout (config -> timeout & WDT_TIMEOUT_MASK );
181+ set_interrupt_enabled (config -> mode == WDT_MODE_INTERRUPT_RESET );
186182 wdt_esp32_seal ();
187183
188184 wdt_esp32_reload (dev );
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