@@ -124,7 +124,6 @@ static void set_interrupt_enabled(bool setting)
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{
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volatile u32_t * intr_enable_reg = (u32_t * )TIMG_INT_ENA_TIMERS_REG (1 );
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- wdt_esp32_unseal ();
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if (setting ) {
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* intr_enable_reg |= TIMG_WDT_INT_ENA ;
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@@ -135,7 +134,6 @@ static void set_interrupt_enabled(bool setting)
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* intr_enable_reg &= ~TIMG_WDT_INT_ENA ;
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irq_disable (CONFIG_WDT_ESP32_IRQ );
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}
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- wdt_esp32_seal ();
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}
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static int wdt_esp32_set_config (struct device * dev , struct wdt_config * config )
@@ -160,29 +158,27 @@ static int wdt_esp32_set_config(struct device *dev, struct wdt_config *config)
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if (config -> mode == WDT_MODE_RESET ) {
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/* Warm reset on timeout */
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- v |= TIMG_WDT_STG_SEL_RESET_CPU <<TIMG_WDT_STG0_S ;
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+ v |= TIMG_WDT_STG_SEL_RESET_SYSTEM <<TIMG_WDT_STG0_S ;
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v |= TIMG_WDT_STG_SEL_OFF <<TIMG_WDT_STG1_S ;
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/* Disable interrupts for this mode. */
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- v &= ~TIMG_WDT_LEVEL_INT_EN ;
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-
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- set_interrupt_enabled (false);
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+ v &= ~(TIMG_WDT_LEVEL_INT_EN | TIMG_WDT_EDGE_INT_EN );
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} else if (config -> mode == WDT_MODE_INTERRUPT_RESET ) {
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/* Interrupt first, and warm reset if not reloaded */
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v |= TIMG_WDT_STG_SEL_INT <<TIMG_WDT_STG0_S ;
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- v |= TIMG_WDT_STG_SEL_RESET_CPU <<TIMG_WDT_STG1_S ;
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+ v |= TIMG_WDT_STG_SEL_RESET_SYSTEM <<TIMG_WDT_STG1_S ;
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/* Use level-triggered interrupts. */
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v |= TIMG_WDT_LEVEL_INT_EN ;
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-
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- set_interrupt_enabled (true);
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+ v &= ~TIMG_WDT_EDGE_INT_EN ;
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} else {
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return - EINVAL ;
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}
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wdt_esp32_unseal ();
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* reg = v ;
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adjust_timeout (config -> timeout & WDT_TIMEOUT_MASK );
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+ set_interrupt_enabled (config -> mode == WDT_MODE_INTERRUPT_RESET );
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wdt_esp32_seal ();
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wdt_esp32_reload (dev );
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