| 
 | 1 | +.. _stm32mp157c_dk2_board:  | 
 | 2 | + | 
 | 3 | +ST STM32MP157C-DK2 Discovery  | 
 | 4 | +############################  | 
 | 5 | + | 
 | 6 | +Overview  | 
 | 7 | +********  | 
 | 8 | + | 
 | 9 | +The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157  | 
 | 10 | +multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.  | 
 | 11 | +Zephyr OS is ported to run on the Cortex®-M4 core.  | 
 | 12 | + | 
 | 13 | +- Common features:  | 
 | 14 | + | 
 | 15 | +  - STM32MP157:  | 
 | 16 | + | 
 | 17 | +    - Arm®-based dual Cortex®-A7 32 bits  | 
 | 18 | +    - Cortex®-M4 32 bits  | 
 | 19 | +    - embedded SRAM (448 Kbytes) for Cortex®-M4.  | 
 | 20 | + | 
 | 21 | +  - ST PMIC STPMIC1A  | 
 | 22 | +  - 4-Gbit DDR3L, 16 bits, 533 MHz  | 
 | 23 | +  - 1-Gbps Ethernet (RGMII) compliant with IEEE-802.3ab  | 
 | 24 | +  - USB OTG HS  | 
 | 25 | +  - Audio CODEC, with a stereo headset jack, including analog microphone input  | 
 | 26 | +  - 4 user LEDs  | 
 | 27 | +  - 2 user and reset push-buttons, 1 wake-up button  | 
 | 28 | +  - 5 V / 3 A USB Type-CTM power supply input (not provided)  | 
 | 29 | +  - Board connectors:  | 
 | 30 | + | 
 | 31 | +    - Ethernet RJ45  | 
 | 32 | +    - 4 USB Host Type-A  | 
 | 33 | +    - USB Type-C  | 
 | 34 | +    - DRP MIPI DSI HDMI  | 
 | 35 | +    - Stereo headset jack including analog microphone input  | 
 | 36 | +    - microSD card  | 
 | 37 | +    - GPIO expansion connector (Raspberry Pi® shields capability)  | 
 | 38 | +    - ArduinoTM Uno V3 expansion connectors  | 
 | 39 | +    - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration  | 
 | 40 | +      capability: Virtual COM port and debug port  | 
 | 41 | + | 
 | 42 | +- Board-specific features:  | 
 | 43 | + | 
 | 44 | +  - 4" TFT 480×800 pixels with LED backlight, MIPI DSI interface, and capacitive  | 
 | 45 | +    touch panel  | 
 | 46 | +  - Wi-Fi® 802.11b/g/n  | 
 | 47 | +  - Bluetooth® Low Energy 4.1  | 
 | 48 | + | 
 | 49 | +.. image:: img/en.stm32mp157c-dk2.jpg  | 
 | 50 | +     :width: 600px  | 
 | 51 | +     :align: center  | 
 | 52 | +     :height: 526px  | 
 | 53 | +     :alt: STM32MP157C-DK2 Discovery  | 
 | 54 | + | 
 | 55 | +More information about the board can be found at the  | 
 | 56 | +`STM32P157C Discovery website`_.  | 
 | 57 | + | 
 | 58 | +Hardware  | 
 | 59 | +********  | 
 | 60 | + | 
 | 61 | +The STM32MP157 SoC provides the following hardware capabilities:  | 
 | 62 | + | 
 | 63 | +- Core:  | 
 | 64 | + | 
 | 65 | +  - 32-bit dual-core Arm® Cortex®-A7  | 
 | 66 | + | 
 | 67 | +    - L1 32-Kbyte I / 32-Kbyte D for each core  | 
 | 68 | +    - 256-Kbyte unified level 2 cache  | 
 | 69 | +    - Arm® NEON™ and Arm® TrustZone®  | 
 | 70 | + | 
 | 71 | +  - 32-bit Arm® Cortex®-M4 with FPU/MPU  | 
 | 72 | + | 
 | 73 | +    - Up to 209 MHz (Up to 703 CoreMark®)  | 
 | 74 | + | 
 | 75 | +- Memories:  | 
 | 76 | + | 
 | 77 | +  - External DDR memory up to 1 Gbyte.  | 
 | 78 | +  - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +  | 
 | 79 | +    64 KB of AHB SRAM in backup domain.  | 
 | 80 | +  - Dual mode Quad-SPI memory interface  | 
 | 81 | +  - Flexible external memory controller with up to 16-bit data bus  | 
 | 82 | + | 
 | 83 | +- Security/safety:  | 
 | 84 | + | 
 | 85 | +  - Secure boot, TrustZone® peripherals with Cortex®-M4 resources isolation  | 
 | 86 | + | 
 | 87 | + | 
 | 88 | +- Clock management:  | 
 | 89 | + | 
 | 90 | +  - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz  | 
 | 91 | +    LSI oscillator  | 
 | 92 | +  - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator  | 
 | 93 | +  - 6 × PLLs with fractional mode  | 
 | 94 | + | 
 | 95 | +- General-purpose input/outputs:  | 
 | 96 | + | 
 | 97 | +  - Up to 176 I/O ports with interrupt capability  | 
 | 98 | + | 
 | 99 | +- Interconnect matrix  | 
 | 100 | + | 
 | 101 | +- 3 DMA controllers  | 
 | 102 | + | 
 | 103 | +- Communication peripherals:  | 
 | 104 | + | 
 | 105 | +  - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)  | 
 | 106 | +  - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)  | 
 | 107 | +  - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)  | 
 | 108 | +  - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)  | 
 | 109 | +  - SPDIF Rx with 4 inputs  | 
 | 110 | +  - HDMI-CEC interface  | 
 | 111 | +  - MDIO Slave interface  | 
 | 112 | +  - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)  | 
 | 113 | +  - 2 × CAN controllers supporting CAN FD protocol, TTCAN capiblity  | 
 | 114 | +  - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously  | 
 | 115 | +  - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)  | 
 | 116 | +  - 8- to 14-bit camera interface up to 140 Mbyte/s  | 
 | 117 | +  - 6 analog peripherals  | 
 | 118 | +  - 2 × ADCs with 16-bit max. resolution.  | 
 | 119 | +  - 1 × temperature sensor  | 
 | 120 | +  - 2 × 12-bit D/A converters (1 MHz)  | 
 | 121 | +  - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6  | 
 | 122 | +    filters  | 
 | 123 | +  - Internal or external ADC/DAC reference VREF+  | 
 | 124 | + | 
 | 125 | +- Graphics:  | 
 | 126 | + | 
 | 127 | +  - 3D GPU: Vivante® - OpenGL® ES 2.0  | 
 | 128 | +  - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps  | 
 | 129 | +  - MIPI® DSI 2 data lanes up to 1 GHz each  | 
 | 130 | + | 
 | 131 | +- Timers:  | 
 | 132 | + | 
 | 133 | +  - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature  | 
 | 134 | +    (incremental) encoder input  | 
 | 135 | +  - 2 × 16-bit advanced motor control timers  | 
 | 136 | +  - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)  | 
 | 137 | +  - 5 × 16-bit low-power timers  | 
 | 138 | +  - RTC with sub-second accuracy and hardware calendar  | 
 | 139 | +  - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)  | 
 | 140 | +  - 1 × SysTick Cortex®-M4 timer  | 
 | 141 | + | 
 | 142 | +- Hardware acceleration:  | 
 | 143 | + | 
 | 144 | +  - AES 128, 192, 256, TDES  | 
 | 145 | +  - HASH (MD5, SHA-1, SHA224, SHA256), HMAC  | 
 | 146 | +  - 2 × true random number generator (3 oscillators each)  | 
 | 147 | +  - 2 × CRC calculation unit  | 
 | 148 | + | 
 | 149 | +- Debug mode:  | 
 | 150 | + | 
 | 151 | +  - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces  | 
 | 152 | +  - 8-Kbyte embedded trace buffer  | 
 | 153 | +  - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user  | 
 | 154 | + | 
 | 155 | +More information about STM32P157C can be found here:  | 
 | 156 | + | 
 | 157 | +- `STM32MP157C on www.st.com`_  | 
 | 158 | +- `STM32MP157C reference manual`_  | 
 | 159 | + | 
 | 160 | +Supported Features  | 
 | 161 | +==================  | 
 | 162 | + | 
 | 163 | +The Zephyr stm32mp157c_dk2 board configuration supports the following hardware  | 
 | 164 | +features:  | 
 | 165 | + | 
 | 166 | ++-----------+------------+-------------------------------------+  | 
 | 167 | +| Interface | Controller | Driver/Component                    |  | 
 | 168 | ++===========+============+=====================================+  | 
 | 169 | +| NVIC      | on-chip    | nested vector interrupt controller  |  | 
 | 170 | ++-----------+------------+-------------------------------------+  | 
 | 171 | + | 
 | 172 | +The default configuration can be found in the defconfig file:  | 
 | 173 | +``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig``  | 
 | 174 | + | 
 | 175 | + | 
 | 176 | +Connections and IOs  | 
 | 177 | +===================  | 
 | 178 | + | 
 | 179 | +STM32MP157C-DK2 Discovery Board schematic is available here:  | 
 | 180 | +`STM32MP157C Discovery board schematics`_.  | 
 | 181 | + | 
 | 182 | + | 
 | 183 | +System Clock  | 
 | 184 | +------------  | 
 | 185 | + | 
 | 186 | +The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.  | 
 | 187 | + | 
 | 188 | +Serial Port  | 
 | 189 | +-----------  | 
 | 190 | + | 
 | 191 | +The STM32MP157C-DK2 Discovery board has 8 U(S)ARTs.  | 
 | 192 | +The Zephyr console output is assigned by default to the ram console to be dumped  | 
 | 193 | +by the Linux Remoteproc Framework on Cortex®-A7 core. The UART 4 can enabled as  | 
 | 194 | +Cortex®-M4 console.  | 
 | 195 | + | 
 | 196 | +Programming and Debugging  | 
 | 197 | +*************************  | 
 | 198 | +The STM32MP157C doesn't have QSPI flash for the Cortex®-M4  and it needs to be  | 
 | 199 | +started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the  | 
 | 200 | +Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.  | 
 | 201 | +The Cortex®-A7 can perform these steps at bootloader level or after the Linux  | 
 | 202 | +system has booted.  | 
 | 203 | + | 
 | 204 | +The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at  | 
 | 205 | +address 0x00000000 (RETRAM), the vector table should be loaded at this address  | 
 | 206 | +These are the memory mappings for Cortex®-A7 and Cortex®-M4:  | 
 | 207 | + | 
 | 208 | ++------------+-----------------------+------------------------+----------------+  | 
 | 209 | +| Region     | Cortex®-A7            | Cortex®-M4             | Size           |  | 
 | 210 | ++============+=======================+========================+================+  | 
 | 211 | +| RETRAM     | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF  | 64KB           |  | 
 | 212 | ++------------+-----------------------+------------------------+----------------+  | 
 | 213 | +| MCUSRAM    | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF  | 384KB          |  | 
 | 214 | ++------------+-----------------------+------------------------+----------------+  | 
 | 215 | +| DDR        | 0xC0000000-0xFFFFFFFF |                        | up to 1 GB     |  | 
 | 216 | ++------------+-----------------------+------------------------+----------------+  | 
 | 217 | + | 
 | 218 | + | 
 | 219 | +Refer to `stm32mp157c boot Cortex-M4 firmware`_ wiki page for instruction  | 
 | 220 | +to load and start the Cortex-M4 firmware.  | 
 | 221 | + | 
 | 222 | +Debugging  | 
 | 223 | +=========  | 
 | 224 | + | 
 | 225 | +You can debug an application using OpenOCD and GDB. The Solution proposed below  | 
 | 226 | +is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux  | 
 | 227 | +environment. The firmware must first be loaded by the Cortex®-A7. Developer  | 
 | 228 | +then attachs the debugger to the running Zephyr using OpenOCD.  | 
 | 229 | + | 
 | 230 | +Prerequisite  | 
 | 231 | +------------  | 
 | 232 | +install `stm32mp1 developer package`_.  | 
 | 233 | + | 
 | 234 | +1) start OpenOCD in a dedicated terminal  | 
 | 235 | + | 
 | 236 | +   - Start up the  sdk environment::  | 
 | 237 | + | 
 | 238 | +      source <SDK installation directory>/environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi  | 
 | 239 | + | 
 | 240 | +   - Start OpenOCD::  | 
 | 241 | + | 
 | 242 | +      ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_dk2.cfg  | 
 | 243 | + | 
 | 244 | +2) run gdb in Zephyr environment  | 
 | 245 | + | 
 | 246 | +   .. code-block:: console  | 
 | 247 | +
  | 
 | 248 | +      # On Linux  | 
 | 249 | +      cd $ZEPHYR_BASE/samples/hello_world  | 
 | 250 | +      mkdir -p build && cd build  | 
 | 251 | +
  | 
 | 252 | +      # Use cmake to configure a Ninja-based build system:  | 
 | 253 | +      cmake -GNinja -DBOARD=stm32mp157_dk2 ..  | 
 | 254 | +
  | 
 | 255 | +      # Now run ninja on the generated build system:  | 
 | 256 | +      ninja debug  | 
 | 257 | +
  | 
 | 258 | +.. _STM32P157C Discovery website:  | 
 | 259 | +   https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/stm32mp157c-dk2.html  | 
 | 260 | + | 
 | 261 | +.. _STM32MP157C Discovery board User Manual:  | 
 | 262 | +   https://www.st.com/resource/en/user_manual/dm00591354.pdf  | 
 | 263 | + | 
 | 264 | +.. _STM32MP157C Discovery board schematics:  | 
 | 265 | +   https://www.st.com/resource/en/schematic_pack/mb1272-dk2-c01_schematic.pdf  | 
 | 266 | + | 
 | 267 | +.. _STM32MP157C on www.st.com:  | 
 | 268 | +   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157c.html  | 
 | 269 | + | 
 | 270 | +.. _STM32MP157C reference manual:  | 
 | 271 | +   https://www.st.com/resource/en/reference_manual/DM00327659.pdf  | 
 | 272 | + | 
 | 273 | +.. _stm32mp1 developer package:  | 
 | 274 | +   https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK  | 
 | 275 | + | 
 | 276 | +.. _stm32mp157c boot Cortex-M4 firmware:  | 
 | 277 | +   https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework  | 
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