boards: stm32l562e_dk: Add non secure target

This commit adds a second target for the stm32l562e_dk board.
The non secure target can be configured for TFM IPC application.

Signed-off-by: Yestin Sun <[email protected]>

Author: yestin

boards/arm/stm32l562e_dk/CMakeLists.txt

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "zephyr")
+  set(COMPILER_FULL_PATH ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin/arm-zephyr-eabi-gcc)
+elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "gnuarmemb")
+  set(COMPILER_FULL_PATH ${GNUARMEMB_TOOLCHAIN_PATH}/bin/arm-none-eabi-gcc)
+endif()
+
+if(CONFIG_BUILD_WITH_TFM)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts
+    #Execute post build script postbuild.sh
+    COMMAND ${CMAKE_BINARY_DIR}/tfm/postbuild.sh ${COMPILER_FULL_PATH}
+  )
+endif()

boards/arm/stm32l562e_dk/Kconfig.defconfig

@@ -32,4 +32,16 @@ config BT_HCI_VS_EXT
 
 endif # BT
 
+if TRUSTED_EXECUTION_NONSECURE
+
+# Get flash configuration for NS image from dts flash partition
+config USE_DT_CODE_PARTITION
+	default y
+
+config TFM_ISOLATION_LEVEL
+	default 2
+	depends on BUILD_WITH_TFM
+
+endif # TRUSTED_EXECUTION_NONSECURE
+
 endif # BOARD_STM32L562E_DK

boards/arm/stm32l562e_dk/board.cmake

@@ -1,3 +1,13 @@
+if(CONFIG_BUILD_WITH_TFM)
+  set(TFM_FLASH_BASE_ADDRESS 0x0C000000)
+
+  if (CONFIG_HAS_FLASH_LOAD_OFFSET)
+    MATH(EXPR TFM_HEX_BASE_ADDRESS_NS "${TFM_FLASH_BASE_ADDRESS}+${CONFIG_FLASH_LOAD_OFFSET}")
+  else()
+    set(TFM_HEX_BASE_ADDRESS_NS ${TFM_TFM_FLASH_BASE_ADDRESS})
+  endif()
+endif()
+
 set_ifndef(BOARD_DEBUG_RUNNER pyocd)
 set_ifndef(BOARD_FLASH_RUNNER pyocd)
 

boards/arm/stm32l562e_dk/doc/index.rst

@@ -166,6 +166,8 @@ The Zephyr stm32l562e_dk board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| TrustZone | on-chip    | Trusted Firmware-M                  |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
@@ -254,6 +256,20 @@ You should see the following message on the console:
 
    Hello World! stm32l562e_dk
 
+Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
+-----------------------------------------------------------------------------
+
+The TF-M integration sample :ref:`tfm_ipc` can be run on a STM32L562E-DK Discovery,
+using the ``stm32l562e_dk_ns`` target. When building a ``*_ns`` image with TF-M,
+a ``build/tfm/postbuild.sh`` bash script will be run automatically as a post-build step
+to make some required flash layout changes. The ``build/tfm/regression.sh`` script will
+need to be run to perform device initialization, and then run ``west flash --hex-file build/tfm_merged.hex``
+to flash the board.
+
+Check the ``build/tfm`` directory to ensure that the commands required by these scripts
+(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI``
+used for initialization is available in the PATH.
+
 Debugging
 =========
 

boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Yestin Sun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "stm32l562e_dk_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32L562E-DK Discovery board";
+	compatible = "st,stm32l562e-dk";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		led0 = &green_led_10;
+		sw0 = &user_button;
+	};
+};

boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml

@@ -0,0 +1,13 @@
+identifier: stm32l562e_dk_ns
+name: ST STM32L562E-DK Discovery non secure
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - i2c
+  - lsm6dso
+ram: 192
+flash: 512

boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig

@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_STM32L5X=y
+CONFIG_SOC_STM32L562XX=y
+# 110MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=110000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# enable pinmux
+CONFIG_PINMUX=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+# SYSCLK selection
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# PLL configuration
+CONFIG_CLOCK_STM32_PLL_SRC_MSI=y
+CONFIG_CLOCK_STM32_MSI_RANGE=6
+# produce 110MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=55
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
+CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=1
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_RUNTIME_NMI=y
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y