soc: mimxrt798s/hifi4: Rework linker and memory defs

Rename symbols so that they reflect purpose of defined memory regions.
Point region symbols to nodes in the DT. Move bogus IDT section before
DSP's ITCM. Move common ROM and RAM sections before the heap.

The move had to be done as these sections and the heap did overlap.

Signed-off-by: Vit Stanicek <[email protected]>

Author: VitekST

soc/nxp/imxrt/imxrt7xx/hifi4/include/soc/memory.h

@@ -1,33 +1,43 @@
 /*
- * Copyright 2024 NXP
+ * Copyright (c) 2023 Google LLC.
+ * Copyright 2024, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef __XTENSA_MEMORY_H__
 #define __XTENSA_MEMORY_H__
 
-#include <zephyr/autoconf.h>
+#include <zephyr/devicetree.h>
 
-#define IRAM_RESERVE_HEADER_SPACE 0x400
+#define TEXT_BASE (DT_REG_ADDR(DT_NODELABEL(adsp_text)))
+#define TEXT_SIZE (DT_REG_SIZE(DT_NODELABEL(adsp_text)))
+#define DATA_BASE (DT_REG_ADDR(DT_NODELABEL(adsp_data)))
+#define DATA_SIZE (DT_REG_SIZE(DT_NODELABEL(adsp_data)))
+#define RESET_BASE (DT_REG_ADDR(DT_NODELABEL(adsp_reset)))
+#define RESET_SIZE (DT_REG_SIZE(DT_NODELABEL(adsp_reset)))
 
-#define IRAM_BASE 0x24020000
-#define IRAM_SIZE 0x10000
+#if TEXT_BASE == 0 || TEXT_SIZE == 0
+#error "Text memory region is improperly defined - missing adsp_text in DT?"
+#endif
 
-#define DRAM_BASE 0x24000000
-#define DRAM_SIZE 0x10000
+#if DATA_BASE == 0 || DATA_SIZE == 0
+#error "Data memory region is improperly defined - missing adsp_data in DT?"
+#endif
 
-#define SDRAM0_BASE 0x20200000
-#define SDRAM0_SIZE 0xFFFFF
+#if RESET_BASE == 0 || RESET_SIZE == 0
+#error "Reset memory region is improperly defined - missing adsp_reset in DT?"
+#endif
 
-/* The reset vector address in IRAM and its size. */
-#define XCHAL_RESET_VECTOR0_PADDR_IRAM IRAM_BASE
-#define MEM_RESET_TEXT_SIZE            (0x2E0)
+/* The reset vector address in SRAM and its size. */
+#define XCHAL_RESET_VECTOR0_PADDR_IRAM (RESET_BASE)
+#define MEM_RESET_TEXT_SIZE            (0x2e0)
 #define MEM_RESET_LIT_SIZE             (0x120)
 
 /* Base address of all interrupt vectors in IRAM. */
-#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
+#define XCHAL_VECBASE_RESET_PADDR_IRAM (TEXT_BASE)
 #define MEM_VECBASE_LIT_SIZE           (0x178)
+
 /* Vector and literal sizes. */
 #define MEM_VECT_LIT_SIZE  (0x4)
 #define MEM_VECT_TEXT_SIZE (0x1C)
@@ -42,13 +52,13 @@
 #define XCHAL_USER_VECTOR_PADDR_IRAM      (XCHAL_INT_VECTOR_ADDR(0x21C))
 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
 
-/* Location for the intList section which is later used to construct the
+
+/* Size and location of the intList section. Later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
- * section will be stripped off in the final image.
+ * section will be stripped off in the final image. Situated before the DSP's
+ * ITCM - prevents memory region inflation in zephyr_pre0.elf.
  */
-#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
-
-/* Size of the Interrupt Descriptor Table (IDT). */
 #define IDT_SIZE (0x2000)
+#define IDT_BASE (RESET_BASE - IDT_SIZE)
 
 #endif