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Glauber Maroto Ferreiracfriedt
Glauber Maroto Ferreira
authored and
cfriedt
committed
soc: riscv: esp32c3: drivers: flash: add support
to host SPI Flash driver. Signed-off-by: Glauber Maroto Ferreira <[email protected]>
1 parent dcf26d7 commit 1af506d

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8 files changed

+76
-15
lines changed

8 files changed

+76
-15
lines changed

‎boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
zephyr,sram = &sram0;
1717
zephyr,console = &uart0;
1818
zephyr,shell-uart = &uart0;
19+
zephyr,flash = &flash0;
1920
};
2021

2122
aliases {

‎drivers/flash/Kconfig.esp32

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ config SOC_FLASH_ESP32
66
default y
77
select FLASH_HAS_DRIVER_ENABLED
88
select FLASH_HAS_PAGE_LAYOUT
9-
depends on SOC_ESP32 || SOC_ESP32S2
9+
depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3
1010
help
1111
Enable ESP32 internal flash driver.
1212

‎drivers/flash/flash_esp32.c

Lines changed: 46 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,24 @@
1010
#define FLASH_WRITE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, write_block_size)
1111
#define FLASH_ERASE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, erase_block_size)
1212

13+
/*
14+
* HAL includes go first to
15+
* avoid BIT macro redefinition
16+
*/
17+
#include <esp_spi_flash.h>
18+
#include <hal/spi_ll.h>
19+
#include <hal/spi_flash_ll.h>
20+
#include <hal/spi_flash_hal.h>
21+
#include <soc/spi_struct.h>
22+
#include <spi_flash_defs.h>
23+
1324
#include <kernel.h>
1425
#include <device.h>
1526
#include <stddef.h>
1627
#include <string.h>
1728
#include <errno.h>
1829
#include <drivers/flash.h>
1930
#include <soc.h>
20-
#include <esp_spi_flash.h>
21-
#include <hal/spi_ll.h>
22-
#include <hal/spi_flash_ll.h>
23-
#include <hal/spi_flash_hal.h>
24-
#include <soc/spi_struct.h>
25-
#include <spi_flash_defs.h>
2631

2732
#if defined(CONFIG_SOC_ESP32)
2833
#include "soc/dport_reg.h"
@@ -33,6 +38,13 @@
3338
#include "soc/spi_mem_reg.h"
3439
#include "esp32s2/rom/cache.h"
3540
#include "esp32s2/rom/spi_flash.h"
41+
#elif defined(CONFIG_SOC_ESP32C3)
42+
#include "soc/spi_periph.h"
43+
#include "soc/spi_mem_reg.h"
44+
#include "soc/dport_access.h"
45+
#include "esp32c3/dport_access.h"
46+
#include "esp32c3/rom/cache.h"
47+
#include "esp32c3/rom/spi_flash.h"
3648
#endif
3749

3850
#include "soc/mmu.h"
@@ -56,7 +68,15 @@ static const struct flash_parameters flash_esp32_parameters = {
5668

5769
#define DEV_DATA(dev) ((struct flash_esp32_dev_data *const)(dev)->data)
5870
#define DEV_CFG(dev) ((const struct flash_esp32_dev_config *const)(dev)->config)
71+
72+
#if !defined(CONFIG_SOC_ESP32C3)
5973
#define SPI1_EXTRA_DUMMIES (g_rom_spiflash_dummy_len_plus[1])
74+
#else
75+
#define SPI1_EXTRA_DUMMIES ((uint8_t)((rom_spiflash_legacy_data->dummy_len_plus)[1]))
76+
#define SPI_FREAD_QIO 0
77+
#define SPI_FREAD_DIO 0
78+
#endif
79+
6080
#define MAX_BUFF_ALLOC_RETRIES 5
6181
#define MAX_READ_CHUNK 16384
6282
#define MAX_WRITE_CHUNK 8192
@@ -67,12 +87,17 @@ static const struct flash_parameters flash_esp32_parameters = {
6787
#define HOST_FLASH_CONTROLLER SPI0
6888
#define HOST_FLASH_RDSR SPI_FLASH_RDSR
6989
#define HOST_FLASH_FASTRD SPI_FASTRD_MODE
70-
#elif defined(CONFIG_SOC_ESP32S2)
90+
#elif defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
7191
#define HOST_FLASH_CONTROLLER SPIMEM0
7292
#define HOST_FLASH_RDSR SPI_MEM_FLASH_RDSR
7393
#define HOST_FLASH_FASTRD SPI_MEM_FASTRD_MODE
7494
#endif
7595

96+
#if defined(CONFIG_SOC_ESP32C3)
97+
static esp_rom_spiflash_chip_t esp_flashchip_info;
98+
#else
99+
#define esp_flashchip_info g_rom_flashchip
100+
#endif
76101

77102
static inline void flash_esp32_sem_take(const struct device *dev)
78103
{
@@ -307,7 +332,7 @@ static int flash_esp32_read(const struct device *dev, off_t address, void *buffe
307332
const spi_flash_guard_funcs_t *guard = spi_flash_guard_get();
308333
uint32_t chip_size = cfg->chip->chip_size;
309334

310-
#if defined(CONFIG_SOC_ESP32S2)
335+
#if defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
311336
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CTRL, 0);
312337
#endif
313338

@@ -426,7 +451,7 @@ static inline bool host_idle(spi_dev_t *hw)
426451
bool idle = spi_flash_ll_host_idle(hw);
427452

428453
idle &= spi_flash_ll_host_idle(&HOST_FLASH_CONTROLLER);
429-
#elif defined(CONFIG_SOC_ESP32S2)
454+
#elif defined(CONFIG_SOC_ESP32S2) || defined(CONFIG_SOC_ESP32C3)
430455
bool idle = spimem_flash_ll_host_idle((spi_mem_dev_t *)hw);
431456

432457
idle &= spimem_flash_ll_host_idle(&HOST_FLASH_CONTROLLER);
@@ -458,7 +483,6 @@ static int wait_idle(const struct device *dev)
458483
static int write_protect(const struct device *dev, bool write_protect)
459484
{
460485
const struct flash_esp32_dev_config *const cfg = DEV_CFG(dev);
461-
uint32_t flash_status = 0;
462486

463487
wait_idle(dev);
464488

@@ -470,12 +494,14 @@ static int write_protect(const struct device *dev, bool write_protect)
470494
if (rc != 0) {
471495
return rc;
472496
}
497+
#if !defined(CONFIG_SOC_ESP32C3)
498+
uint32_t flash_status = 0;
473499

474500
/* make sure the flash is ready for writing */
475501
while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
476502
read_status(dev, &flash_status);
477503
}
478-
504+
#endif
479505
return 0;
480506
}
481507

@@ -670,7 +696,6 @@ static int flash_esp32_write(const struct device *dev,
670696
guard->start();
671697
flash_esp32_flush_cache(address, length);
672698
guard->end();
673-
674699
flash_esp32_sem_give(dev);
675700

676701
return rc;
@@ -777,6 +802,14 @@ static int flash_esp32_init(const struct device *dev)
777802
{
778803
struct flash_esp32_dev_data *const dev_data = DEV_DATA(dev);
779804

805+
#if defined(CONFIG_SOC_ESP32C3)
806+
spiflash_legacy_data_t *legacy_data = rom_spiflash_legacy_data;
807+
808+
esp_flashchip_info.chip_size = legacy_data->chip.chip_size;
809+
esp_flashchip_info.sector_size = legacy_data->chip.sector_size;
810+
esp_flashchip_info.page_size = legacy_data->chip.page_size;
811+
#endif
812+
780813
k_sem_init(&dev_data->sem, 1, 1);
781814

782815
return 0;
@@ -796,7 +829,7 @@ static struct flash_esp32_dev_data flash_esp32_data;
796829

797830
static const struct flash_esp32_dev_config flash_esp32_config = {
798831
.controller = (spi_dev_t *) DT_INST_REG_ADDR(0),
799-
.chip = &g_rom_flashchip
832+
.chip = &esp_flashchip_info
800833
};
801834

802835
DEVICE_DT_INST_DEFINE(0, flash_esp32_init,

‎dts/riscv/espressif/esp32c3.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#size-cells = <1>;
1414
chosen {
1515
zephyr,entropy = &trng0;
16+
zephyr,flash-controller = &flash;
1617
};
1718

1819
cpus {
@@ -70,6 +71,23 @@
7071
status = "ok";
7172
};
7273

74+
flash: flash-controller@60002000 {
75+
compatible = "espressif,esp32-flash-controller";
76+
label = "FLASH_CTRL";
77+
reg = <0x60002000 0x1000>;
78+
79+
#address-cells = <1>;
80+
#size-cells = <1>;
81+
82+
flash0: flash@0 {
83+
compatible = "soc-nv-flash";
84+
label = "FLASH_ESP32C3";
85+
reg = <0 0x400000>;
86+
erase-block-size = <4096>;
87+
write-block-size = <4>;
88+
};
89+
};
90+
7391
gpio0: gpio@60004000 {
7492
compatible = "espressif,esp32-gpio";
7593
gpio-controller;

‎soc/riscv/esp32c3/linker.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ SECTIONS
118118
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
119119
*libkernel.a:(.literal .text .literal.* .text.*)
120120
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
121+
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
121122
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
122123
*libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)
123124
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
@@ -175,6 +176,7 @@ SECTIONS
175176
*libzephyr.a:log_core.*(.rodata .rodata.*)
176177
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
177178
*libzephyr.a:log_output.*(.rodata .rodata.*)
179+
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
178180
. = ALIGN(4);
179181
__esp_log_const_start = .;
180182
KEEP(*(SORT(.log_const_*)));

‎soc/riscv/esp32c3/soc.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,10 @@ void __attribute__((section(".iram1"))) __start(void)
9797
REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
9898
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
9999

100+
#if CONFIG_SOC_FLASH_ESP32
101+
spi_flash_guard_set(&g_flash_guard_default_ops);
102+
#endif
103+
100104
/*Initialize the esp32c3 interrupt controller */
101105
esp_intr_initialize();
102106

‎soc/riscv/esp32c3/soc.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,9 @@ extern STATUS esp_rom_uart_rx_one_char(uint8_t *chr);
4343
extern void esp_rom_ets_set_user_start(uint32_t start);
4444
extern void esprv_intc_int_set_threshold(int priority_threshold);
4545
uint32_t soc_intr_get_next_source(void);
46+
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
47+
extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
48+
extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data;
4649

4750
#endif /* _ASMLANGUAGE */
4851

‎west.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ manifest:
6767
groups:
6868
- hal
6969
- name: hal_espressif
70-
revision: a360365cb7858826809c82e375524ee5faf497ac
70+
revision: 7c46a3fc5b336199392cba0f66c3c27d5fe9025c
7171
path: modules/hal/espressif
7272
west-commands: west/west-commands.yml
7373
groups:

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