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arch: riscv: Add support for Xuantie CPUs
Adds some support for xuantie CPU, namely cache control Signed-off-by: Camille BAUD <[email protected]>
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‎arch/riscv/Kconfig‎

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@@ -526,5 +526,6 @@ config RISCV_NO_MTVAL_ON_FP_TRAP
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to handle FP exceptions.
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rsource "Kconfig.isa"
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rsource "core/Kconfig"
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endmenu

‎arch/riscv/core/CMakeLists.txt‎

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@@ -42,3 +42,5 @@ if(CONFIG_GEN_SW_ISR_TABLE)
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zephyr_linker_sources(RODATA swi_tables.ld)
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endif()
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endif()
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add_subdirectory_ifdef(CONFIG_XUANTIE xuantie)

‎arch/riscv/core/Kconfig‎

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# RISC-V cores configuration options
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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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config XUANTIE
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bool
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help
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This option signifies the use of a CPU of the XuanTie RISC-V family
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rsource "xuantie/Kconfig"

‎arch/riscv/core/xuantie/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/cache.h)
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO cache_xtheadcmo.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO_E907 cache_xtheadcmo_e907.c)

‎arch/riscv/core/xuantie/Kconfig‎

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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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config XUANTIE_E907
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bool
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select XUANTIE
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select GEN_IRQ_VECTOR_TABLE
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select INCLUDE_RESET_VECTOR
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select RISCV_HAS_CLIC
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select RISCV_MACHINE_TIMER
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select RISCV_PRIVILEGED
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_VECTORED_MODE
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if XUANTIE
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config CACHE_XTHEADCMO
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bool
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default y
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select CACHE_MANAGEMENT
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select CPU_HAS_ICACHE
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help
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This option enables cache support for XuanTie family of CPUs using the XTHeadCmo extension
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if CACHE_XTHEADCMO
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config DCACHE_LINE_SIZE
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default 32
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config ICACHE_LINE_SIZE
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default 32
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config CACHE_XTHEADCMO_E907
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bool
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default y
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depends on XUANTIE_E907
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select CPU_HAS_DCACHE
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help
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This option enables the additional XTHeadCmo cache functions for the E907 cores
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endif # CACHE_XTHEADCMO
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endif # XUANTIE

‎arch/riscv/core/xuantie/cache_xtheadcmo.c‎

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/cache.h>
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int arch_dcache_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.iall */
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".insn 0x20000B\n"
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"fence\n"
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);
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return 0;
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}
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static void arch_cache_invalidate_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.ipa a3*/
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".insn 0x2A6800B\n"
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:
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: "r"(address)
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);
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}
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int arch_dcache_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += CONFIG_DCACHE_LINE_SIZE) {
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arch_cache_invalidate_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int arch_icache_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.icache.iall */
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".insn 0x100000B\n"
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"fence\n"
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"fence.i\n"
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);
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return 0;
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}
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static void arch_cache_invalidate_icache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.icache.ipa a3*/
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".insn 0x386800B\n"
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:
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: "r"(address)
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);
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}
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int arch_icache_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += CONFIG_ICACHE_LINE_SIZE) {
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arch_cache_invalidate_icache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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return 0;
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}
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int arch_dcache_flush_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.call */
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".insn 0x10000B\n"
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"fence\n"
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);
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return 0;
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}
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static void arch_cache_clean_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.cpa a3*/
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".insn 0x296800B\n"
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:
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: "r"(address)
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);
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}
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int arch_dcache_flush_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += CONFIG_DCACHE_LINE_SIZE) {
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arch_cache_clean_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int arch_dcache_flush_and_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.ciall */
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".insn 0x30000B\n"
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"fence\n"
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);
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return 0;
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}
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static void arch_cache_clean_invalidate_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.cipa a3*/
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".insn 0x2B6800B\n"
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:
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: "r"(address)
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);
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}
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int arch_dcache_flush_and_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += CONFIG_DCACHE_LINE_SIZE) {
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arch_cache_clean_invalidate_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int arch_icache_flush_all(void)
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{
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return -ENOTSUP;
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}
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int arch_icache_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int arch_icache_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int arch_icache_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}

‎arch/riscv/core/xuantie/cache_xtheadcmo_e907.c‎

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/cache.h>
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/* "a Hardware CSR" */
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#define THEAD_MHCR "0x7C1"
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void arch_icache_enable(void)
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{
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uint32_t tmp;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.icache.iall */
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".insn 0x100000B\n"
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);
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__asm__ volatile(
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"csrr %0, " THEAD_MHCR
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: "=r"(tmp));
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tmp |= (1 << 0);
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__asm__ volatile(
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"csrw " THEAD_MHCR ", %0"
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:
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: "r"(tmp));
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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}
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void arch_dcache_enable(void)
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{
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uint32_t tmp;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.dcache.iall */
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".insn 0x20000B\n"
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);
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__asm__ volatile(
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"csrr %0, " THEAD_MHCR
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: "=r"(tmp));
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tmp |= (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4);
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__asm__ volatile(
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"csrw " THEAD_MHCR ", %0"
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:
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: "r"(tmp));
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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}
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void arch_icache_disable(void)
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{
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uint32_t tmp;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.icache.iall */
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".insn 0x100000B\n"
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);
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__asm__ volatile(
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"csrr %0, " THEAD_MHCR
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: "=r"(tmp));
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tmp &= ~(1 << 0);
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__asm__ volatile(
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"csrw " THEAD_MHCR ", %0"
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:
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: "r"(tmp));
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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}
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void arch_dcache_disable(void)
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{
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uint32_t tmp;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.dcache.iall */
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".insn 0x20000B\n"
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);
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__asm__ volatile(
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"csrr %0, " THEAD_MHCR
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: "=r"(tmp));
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tmp &= ~((1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
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__asm__ volatile(
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"csrw " THEAD_MHCR ", %0"
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:
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: "r"(tmp));
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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}

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