style: drivers: comply with MISRA C:2012 Rule 15.6

Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <[email protected]>

Author: ndrs-pst

drivers/adc/adc_rpi_pico.c

@@ -91,8 +91,9 @@ static inline void adc_clear_errors(void)
 static inline void adc_enable(void)
 {
 	adc_hw->cs = ADC_CS_EN_BITS;
-	while (!(adc_hw->cs & ADC_CS_READY_BITS))
+	while (!(adc_hw->cs & ADC_CS_READY_BITS)) {
 		;
+	}
 }
 
 static int adc_rpi_channel_setup(const struct device *dev,

drivers/adc/adc_smartbond_sdadc.c

@@ -150,8 +150,9 @@ static void adc_context_start_sampling(struct adc_context *ctx)
 	int current_channel = u32_count_trailing_zeros(data->channel_read_mask);
 
 	/* Wait until the SDADC LDO stabilizes */
-	while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk))
+	while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk)) {
 		__NOP();
+	}
 
 	if (ctx->sequence.calibrate) {
 		/* TODO: Add calibration code */

drivers/clock_control/clock_control_npcx.c

@@ -223,8 +223,9 @@ static int npcx_clock_control_init(const struct device *dev)
 		/* Load M and N values into the frequency multiplier */
 		inst_cdcg->HFCGCTRL |= BIT(NPCX_HFCGCTRL_LOAD);
 		/* Wait for stable */
-		while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
+		while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG)) {
 			;
+		}
 	}
 
 	/* Set all clock prescalers of core and peripherals. */

drivers/counter/counter_gecko_stimer.c

@@ -110,8 +110,9 @@ static int counter_gecko_start(const struct device *dev)
 	bool is_top_timer_running = false;
 
 	error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
-	if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true))
+	if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
 		return 0;
+	}
 	struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
 
 	error_code = sl_sleeptimer_start_timer(&top_timer, dev_data->top_data.ticks, top_callback,

drivers/counter/counter_native_posix.c

@@ -181,8 +181,9 @@ static int ctr_set_alarm(const struct device *dev, uint8_t chan_id,
 {
 	ARG_UNUSED(dev);
 
-	if (is_alarm_pending[chan_id])
+	if (is_alarm_pending[chan_id]) {
 		return -EBUSY;
+	}
 
 	uint32_t ticks = alarm_cfg->ticks;
 

drivers/dai/intel/dmic/dmic.c

@@ -76,11 +76,13 @@ static int32_t exp_fixed(int32_t x)
 	int i;
 	int n = 0;
 
-	if (x < Q_CONVERT_FLOAT(-11.5, 27))
+	if (x < Q_CONVERT_FLOAT(-11.5, 27)) {
 		return 0;
+	}
 
-	if (x > Q_CONVERT_FLOAT(7.6245, 27))
+	if (x > Q_CONVERT_FLOAT(7.6245, 27)) {
 		return INT32_MAX;
+	}
 
 	/* x is Q5.27 */
 	xs = x;
@@ -94,8 +96,9 @@ static int32_t exp_fixed(int32_t x)
 	 */
 	z = Q_SHIFT_RND(exp_small_fixed(Q_SHIFT_LEFT(xs, 27, 29)), 23, 20);
 	y = ONE_Q20;
-	for (i = 0; i < (1 << n); i++)
+	for (i = 0; i < (1 << n); i++) {
 		y = (int32_t)Q_MULTSR_32X32((int64_t)y, z, 20, 20, 20);
+	}
 
 	return y;
 }
@@ -104,8 +107,9 @@ static int32_t db2lin_fixed(int32_t db)
 {
 	int32_t arg;
 
-	if (db < Q_CONVERT_FLOAT(-100.0, 24))
+	if (db < Q_CONVERT_FLOAT(-100.0, 24)) {
 		return 0;
+	}
 
 	/* Q8.24 x Q5.27, result needs to be Q5.27 */
 	arg = (int32_t)Q_MULTSR_32X32((int64_t)db, LOG10_DIV20_Q27, 24, 27, 27);
@@ -383,8 +387,9 @@ static int dai_dmic_remove(struct dai_intel_dmic *dmic)
 	 * Note: dai_put() function that calls remove() applies the spinlock
 	 * so it is not needed here to protect access to mask bits.
 	 */
-	if (active_fifos_mask || pause_mask)
+	if (active_fifos_mask || pause_mask) {
 		return 0;
+	}
 
 	/* Disable DMIC clock and power */
 	dai_dmic_en_clk_gating(dmic);
@@ -442,8 +447,9 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
 
 	/* Read SSP timestamp registers */
 	ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
-	if (!ntk)
+	if (!ntk) {
 		goto out;
+	}
 
 	/* NTK was set, get wall clock */
 	tsd->walclk = sys_read64(TS_DMIC_LOCAL_WALCLK);
@@ -456,8 +462,9 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
 
 out:
 	tsd->walclk_rate = cfg->walclk_rate;
-	if (!ntk)
+	if (!ntk) {
 		return -ENODATA;
+	}
 
 	return 0;
 }
@@ -484,8 +491,9 @@ static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
 	 * task associated with each DAI, so we don't need to hold the lock to
 	 * read the value here.
 	 */
-	if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11)
+	if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {
 		return;
+	}
 
 	key = k_spin_lock(&dmic->lock);
 
@@ -659,10 +667,11 @@ static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
 	 * If stop is not for pausing, it is safe to clear the pause bit.
 	 */
 	dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);
-	if (stop_is_pause)
+	if (stop_is_pause) {
 		dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);
-	else
+	} else {
 		dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);
+	}
 
 	for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
 		/* Don't stop CIC yet if one FIFO remains active */

drivers/dai/intel/dmic/dmic.h

@@ -205,11 +205,13 @@ static inline int dmic_get_unmute_ramp_from_samplerate(int rate)
 
 	time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
 		LOGRAMP_TIME_OFFS_Q0;
-	if (time_ms > LOGRAMP_TIME_MAX_MS)
+	if (time_ms > LOGRAMP_TIME_MAX_MS) {
 		return LOGRAMP_TIME_MAX_MS;
+	}
 
-	if (time_ms < LOGRAMP_TIME_MIN_MS)
+	if (time_ms < LOGRAMP_TIME_MIN_MS) {
 		return LOGRAMP_TIME_MIN_MS;
+	}
 
 	return time_ms;
 }

drivers/dai/intel/dmic/dmic_nhlt.c

@@ -668,8 +668,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
 
 	/* Configure clock source */
 	ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source);
-	if (ret)
+	if (ret) {
 		return ret;
+	}
 
 	/* Get OUTCONTROLx configuration */
 	if (num_fifos < 1 || num_fifos > DMIC_HW_FIFOS_MAX) {
@@ -678,8 +679,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
 	}
 
 	for (n = 0; n < DMIC_HW_FIFOS_MAX; n++) {
-		if (!(channel_ctrl_mask & (1 << n)))
+		if (!(channel_ctrl_mask & (1 << n))) {
 			continue;
+		}
 
 		val = *(uint32_t *)p;
 		ret = print_outcontrol(val);
@@ -802,8 +804,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
 #else
 	ret = dai_nhlt_dmic_dai_params_get(dmic);
 #endif
-	if (ret)
+	if (ret) {
 		return ret;
+	}
 
 	LOG_INF("dmic_set_config_nhlt(): enable0 %u, enable1 %u",
 		dmic->enable[0], dmic->enable[1]);

drivers/dai/intel/hda/hda.c

@@ -32,10 +32,13 @@ static int dai_hda_set_config_tplg(struct dai_intel_hda *dp, const void *spec_co
 	struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
 	const struct dai_intel_ipc_hda_params *config = spec_config;
 
-	if (config->channels)
+	if (config->channels) {
 		hda->params.channels = config->channels;
-	if (config->rate)
+	}
+
+	if (config->rate) {
 		hda->params.rate = config->rate;
+	}
 
 	return 0;
 }
@@ -65,8 +68,9 @@ static int dai_hda_config_set(const struct device *dev, const struct dai_config
 {
 	struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
 
-	if (cfg->type == DAI_INTEL_HDA)
+	if (cfg->type == DAI_INTEL_HDA) {
 		return dai_hda_set_config_tplg(dp, bespoke_cfg);
+	}
 
 	return 0;
 }

drivers/dai/intel/ssp/ssp.c

@@ -1999,8 +1999,9 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
 	aux_len = cfg_len - pre_aux_len;
 	aux_ptr = (uint8_t *)blob + pre_aux_len;
 
-	if (aux_len <= 0)
+	if (aux_len <= 0) {
 		return 0;
+	}
 
 	return dai_ssp_parse_tlv(dp, aux_ptr, aux_len);
 }
@@ -2132,17 +2133,20 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
 
 	if (blob15->version == SSP_BLOB_VER_1_5) {
 		err = dai_ssp_parse_aux_data(dp, spec_config);
-		if (err)
+		if (err) {
 			return err;
+		}
 		dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
 		err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
-		if (err)
+		if (err) {
 			return err;
+		}
 	} else {
 		dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
 		err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
-		if (err)
+		if (err) {
 			return err;
+		}
 	}
 
 	ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;