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lines changed Original file line number Diff line number Diff line change
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+ CONFIG_DMA_TRANSFER_CHANNEL_NR_0=4
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+ CONFIG_DMA_TRANSFER_CHANNEL_NR_1=6
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+ CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2
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+
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+ # Required by BDMA which only has access to
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+ # a NOCACHE SRAM4 section. All other DMAs also
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+ # has access to this section.
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+ CONFIG_CODE_DATA_RELOCATION=y
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+ CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
Original file line number Diff line number Diff line change
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+ /*
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+ * Copyright (c) 2025 STMicroelectronics
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+
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+ #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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+
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+ &dma1 {
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+ status = "okay";
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+ };
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+
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+ &dma2 {
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+ status = "okay";
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+ };
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+
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+ tst_dma0: &dmamux1 {
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+ status = "okay";
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+ };
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+
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+ /* The BDMA driver expects the SRAM4 region
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+ * to be non-cachable.
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+ */
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+ &sram4 {
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+ zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
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+ };
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+
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+ &bdma1 {
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+ status = "okay";
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+ };
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+
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+ tst_dma1: &dmamux2 {
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+ status = "okay";
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+ };
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