drivers: counter: rtc: esp32: Add LP TIMER support

Add support to LP TIMER peripheral, for ESP32-C6 and ESP32-H2
RTC counter support.

Signed-off-by: Raffael Rostagno <[email protected]>

Author: Raffael Rostagno

drivers/counter/counter_esp32_rtc.c

@@ -6,10 +6,16 @@
 
 #define DT_DRV_COMPAT espressif_esp32_rtc_timer
 
+#include <soc/soc_caps.h>
+#include <esp_rom_sys.h>
+
+#if SOC_LP_TIMER_SUPPORTED
+#include "hal/lp_timer_ll.h"
+#else
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc.h"
-#include <esp_rom_sys.h>
 #include <hal/rtc_cntl_ll.h>
+#endif
 
 #include <zephyr/device.h>
 #include <zephyr/drivers/counter.h>
@@ -26,6 +32,9 @@ static void counter_esp32_isr(void *arg);
 
 struct counter_esp32_config {
 	struct counter_config_info counter_info;
+#if SOC_LP_TIMER_SUPPORTED
+	lp_timer_dev_t *dev;
+#endif
 	int irq_source;
 	int irq_priority;
 	int irq_flags;
@@ -84,18 +93,37 @@ static int counter_esp32_stop(const struct device *dev)
 
 static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
 {
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+
+	lp_timer_ll_counter_snapshot(cfg->dev);
+
+	*ticks = lp_timer_ll_get_counter_value_low(cfg->dev, 0);
+#else
 	ARG_UNUSED(dev);
 
 	*ticks = (uint32_t) rtc_cntl_ll_get_rtc_time();
+#endif
 
 	return 0;
 }
 
 static int counter_esp32_get_value_64(const struct device *dev, uint64_t *ticks)
 {
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+
+	lp_timer_ll_counter_snapshot(cfg->dev);
+
+	uint32_t lo = lp_timer_ll_get_counter_value_low(cfg->dev, 0);
+	uint32_t hi = lp_timer_ll_get_counter_value_high(cfg->dev, 0);
+
+	*ticks = ((uint64_t)hi << 32 | lo);
+#else
 	ARG_UNUSED(dev);
 
 	*ticks = rtc_cntl_ll_get_rtc_time();
+#endif
 
 	return 0;
 }
@@ -104,6 +132,10 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
 				   const struct counter_alarm_cfg *alarm_cfg)
 {
 	ARG_UNUSED(chan_id);
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+	lp_timer_dev_t *lp_timer = cfg->dev;
+#endif
 	struct counter_esp32_data *data = dev->data;
 	uint64_t now;
 	uint64_t ticks = 0;
@@ -131,6 +163,12 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
 
 	data->ticks = (uint32_t)ticks;
 
+#if SOC_LP_TIMER_SUPPORTED
+	lp_timer_ll_clear_alarm_intr_status(cfg->dev);
+	lp_timer_ll_set_alarm_target(cfg->dev, 0, ticks);
+	lp_timer_ll_set_target_enable(cfg->dev, 0, true);
+	lp_timer->int_en.alarm = 1;
+#else
 	rtc_cntl_ll_set_wakeup_timer(ticks);
 
 	/* RTC main timer set alarm value */
@@ -141,6 +179,7 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
 
 	/* RTC main timer interrupt enable */
 	SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_MAIN_TIMER_INT_ENA);
+#endif
 
 	return 0;
 }
@@ -150,12 +189,21 @@ static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id)
 	ARG_UNUSED(chan_id);
 	struct counter_esp32_data *data = dev->data;
 
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+	lp_timer_dev_t *lp_timer = cfg->dev;
+
+	lp_timer_ll_set_target_enable(cfg->dev, 0, false);
+	lp_timer->int_en.alarm = 0;
+	lp_timer_ll_clear_alarm_intr_status(cfg->dev);
+#else
 	/* RTC main timer set alarm disable */
 	CLEAR_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN);
 
 	/* RTC main timer interrupt disable, and clear interrupt flag */
 	REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
 	SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR);
+#endif
 
 	data->alarm_cfg.callback = NULL;
 	data->alarm_cfg.user_data = NULL;
@@ -177,11 +225,18 @@ static int counter_esp32_set_top_value(const struct device *dev,
 
 static uint32_t counter_esp32_get_pending_int(const struct device *dev)
 {
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+	lp_timer_dev_t *lp_timer = cfg->dev;
+
+	return lp_timer->int_st.alarm;
+#else
 	ARG_UNUSED(dev);
 
 	uint32_t rc = READ_PERI_REG(RTC_CNTL_INT_ST_REG) & RTC_CNTL_MAIN_TIMER_INT_ST;
 
 	return (rc >> RTC_CNTL_MAIN_TIMER_INT_ST_S);
+#endif
 }
 
 /*
@@ -211,6 +266,9 @@ static const struct counter_esp32_config counter_config = {
 		.flags = COUNTER_CONFIG_INFO_COUNT_UP,
 		.channels = 1
 	},
+#if SOC_LP_TIMER_SUPPORTED
+	.dev = (lp_timer_dev_t *)DT_INST_REG_ADDR(0),
+#endif
 	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
 	.irq_source = DT_INST_IRQ_BY_IDX(0, 0, irq),
 	.irq_priority = DT_INST_IRQ_BY_IDX(0, 0, priority),
@@ -237,11 +295,21 @@ static void counter_esp32_isr(void *arg)
 	counter_alarm_callback_t cb = data->alarm_cfg.callback;
 	void *cb_data = data->alarm_cfg.user_data;
 	uint32_t now;
+
+#if SOC_LP_TIMER_SUPPORTED
+	const struct counter_esp32_config *cfg = dev->config;
+	lp_timer_dev_t *lp_timer = cfg->dev;
+
+	if (!lp_timer->int_st.alarm) {
+		return;
+	}
+#else
 	uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG);
 
 	if (!(status & RTC_CNTL_MAIN_TIMER_INT_ST_M)) {
 		return;
 	}
+#endif
 
 	counter_esp32_cancel_alarm(dev, 0);
 	counter_esp32_get_value(dev, &now);