dts: stm32l4: Update AES node for stm32l4 series

The stm32l4 devices were previously assigned the generic STM32 AES driver,
which turned out to be incompatible with the stm32l4 series. This commit
updates the nodes to use the new driver specifically designed for this
series.

Add missing node for stm32l4a6, stm32l4q5, stm32l4s5 and stm32l486 socs.

It appears stm32l4p5 and stm32l496 socs do not have the AES accelerator
present, so the nodes are removed from the dts files.

Signed-off-by: Lucas Dietrich <[email protected]>

Author: lucasdietrich

dts/arm/st/l4/stm32l422.dtsi

@@ -11,7 +11,7 @@
 		compatible = "st,stm32l422", "st,stm32l4", "simple-bus";
 
 		aes: aes@50060000 {
-			compatible = "st,stm32-aes";
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
 			reg = <0x50060000 0x400>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
 			resets = <&rctl STM32_RESET(AHB2, 16U)>;

dts/arm/st/l4/stm32l462.dtsi

@@ -11,7 +11,7 @@
 		compatible = "st,stm32l462", "st,stm32l4", "simple-bus";
 
 		aes: aes@50060000 {
-			compatible = "st,stm32-aes";
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
 			reg = <0x50060000 0x400>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
 			resets = <&rctl STM32_RESET(AHB2, 16U)>;

dts/arm/st/l4/stm32l486.dtsi

@@ -9,5 +9,15 @@
 / {
 	soc {
 		compatible = "st,stm32l486", "st,stm32l4", "simple-bus";
+
+		aes: aes@50060000 {
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			resets = <&rctl STM32_RESET(AHB2, 16U)>;
+			interrupts = <79 0>;
+			interrupt-names = "aes";
+			status = "disabled";
+		};
 	};
 };

dts/arm/st/l4/stm32l496.dtsi

@@ -60,16 +60,6 @@
 			status = "disabled";
 		};
 
-		aes: aes@50060000 {
-			compatible = "st,stm32-aes";
-			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
-			resets = <&rctl STM32_RESET(AHB2, 16U)>;
-			interrupts = <79 0>;
-			interrupt-names = "aes";
-			status = "disabled";
-		};
-
 		usbotg_fs: otgfs@50000000 {
 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;

dts/arm/st/l4/stm32l4a6.dtsi

@@ -9,5 +9,15 @@
 / {
 	soc {
 		compatible = "st,stm32l4a6", "st,stm32l4", "simple-bus";
+
+		aes: aes@50060000 {
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			resets = <&rctl STM32_RESET(AHB2, 16U)>;
+			interrupts = <79 0>;
+			interrupt-names = "aes";
+			status = "disabled";
+		};
 	};
 };

dts/arm/st/l4/stm32l4p5.dtsi

@@ -294,16 +294,6 @@
 			status = "disabled";
 		};
 
-		aes: aes@50060000 {
-			compatible = "st,stm32-aes";
-			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
-			resets = <&rctl STM32_RESET(AHB2, 16U)>;
-			interrupts = <79 0>;
-			interrupt-names = "aes";
-			status = "disabled";
-		};
-
 		usbotg_fs: otgfs@50000000 {
 			compatible = "st,stm32-otgfs";
 			reg = <0x50000000 0x40000>;

dts/arm/st/l4/stm32l4q5.dtsi

@@ -9,5 +9,15 @@
 / {
 	soc {
 		compatible = "st,stm32l4q5", "st,stm32l4", "simple-bus";
+
+		aes: aes@50060000 {
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			resets = <&rctl STM32_RESET(AHB2, 16U)>;
+			interrupts = <79 0>;
+			interrupt-names = "aes";
+			status = "disabled";
+		};
 	};
 };

dts/arm/st/l4/stm32l4s5.dtsi

@@ -9,5 +9,15 @@
 / {
 	soc {
 		compatible = "st,stm32l4s5", "st,stm32l4", "simple-bus";
+
+		aes: aes@50060000 {
+			compatible = "st,stm32l4-aes", "st,stm32-aes";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			resets = <&rctl STM32_RESET(AHB2, 16U)>;
+			interrupts = <79 0>;
+			interrupt-names = "aes";
+			status = "disabled";
+		};
 	};
 };