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nandojvefabiobaltieri
nandojve
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boards: atmel: Fix devicetree style
The Zephyr is implementing a linter to catch devicetree problems. This boards comments are exceptions and are formatted to be compliance with the linter. However due to the exception the linter check was disabled to avoid undesirable formatting and keep the original details in the comments. Signed-off-by: Gerson Fernando Budke <[email protected]>
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4 files changed

+250
-198
lines changed

4 files changed

+250
-198
lines changed

‎boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts‎

Lines changed: 69 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -52,75 +52,87 @@
5252
compatible = "atmel-xplained-pro-header";
5353
#gpio-cells = <2>;
5454
gpio-map-mask = <0xffffffff 0xffffffc0>;
55-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
56-
gpio-map = <0 0 &piob 2 0>, /* AFE AD0 */
57-
<1 0 &piob 3 0>, /* AFE AD1 */
58-
<2 0 &pioa 24 0>, /* GPIO */
59-
<3 0 &pioa 25 0>, /* GPIO */
60-
<4 0 &pioa 15 0>, /* TIOA1 */
61-
<5 0 &pioa 16 0>, /* TIOB1 */
62-
<6 0 &pioa 11 0>, /* WKUP7 */
63-
<7 0 &piod 25 0>, /* GPIO */
64-
<8 0 &pioa 3 0>, /* TWD0 EXTx */
65-
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
66-
<10 0 &pioa 21 0>, /* RXD1 */
67-
<11 0 &pioa 22 0>, /* TXD1 */
68-
<12 0 &piob 14 0>, /* SPI(NPCS1) */
69-
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
70-
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
71-
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
72-
/* GND */
73-
/* +3.3V */
55+
gpio-map-pass-thru = <0 0x3f>;
56+
57+
/* dts-format off */
58+
/* Shared */
59+
gpio-map = <0 0 &piob 2 0>, /* AFE AD0 */
60+
<1 0 &piob 3 0>, /* AFE AD1 */
61+
<2 0 &pioa 24 0>, /* GPIO */
62+
<3 0 &pioa 25 0>, /* GPIO */
63+
<4 0 &pioa 15 0>, /* TIOA1 */
64+
<5 0 &pioa 16 0>, /* TIOB1 */
65+
<6 0 &pioa 11 0>, /* WKUP7 */
66+
<7 0 &piod 25 0>, /* GPIO */
67+
<8 0 &pioa 3 0>, /* TWD0 EXTx */
68+
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
69+
<10 0 &pioa 21 0>, /* RXD1 */
70+
<11 0 &pioa 22 0>, /* TXD1 */
71+
<12 0 &piob 14 0>, /* SPI(NPCS1) */
72+
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
73+
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
74+
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
75+
/* GND */
76+
/* +3.3V */
77+
/* dts-format on */
7478
};
7579

7680
ext2_header: xplained-pro-connector2 {
7781
compatible = "atmel-xplained-pro-header";
7882
#gpio-cells = <2>;
7983
gpio-map-mask = <0xffffffff 0xffffffc0>;
80-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
81-
gpio-map = /*<0 0 - - 0>, - */
82-
/*<1 0 - - 0>, - */
83-
<2 0 &pioe 2 0>, /* GPIO EBDG */
84-
<3 0 &piob 5 0>, /* GPIO EDBG */
85-
<4 0 &piod 21 0>, /* PWMHI1 */
86-
/*<5 0 - - 0>, - */
87-
<6 0 &piod 29 0>, /* GPIO ETH */
88-
<7 0 &piob 4 0>, /* GPIO */
89-
<8 0 &pioa 3 0>, /* TWD0 EXTx */
90-
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
91-
<10 0 &pioa 5 0>, /* URXD1 EXT3 */
92-
<11 0 &pioa 6 0>, /* UTXD1 EXT3 */
93-
<12 0 &piod 23 0>, /* GPIO */
94-
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
95-
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
96-
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
97-
/* GND */
98-
/* +3.3V */
84+
gpio-map-pass-thru = <0 0x3f>;
85+
86+
/* dts-format off */
87+
/* Shared */
88+
gpio-map = /*<0 0 - - 0>, - */
89+
/*<1 0 - - 0>, - */
90+
<2 0 &pioe 2 0>, /* GPIO EBDG */
91+
<3 0 &piob 5 0>, /* GPIO EDBG */
92+
<4 0 &piod 21 0>, /* PWMHI1 */
93+
/*<5 0 - - 0>, - */
94+
<6 0 &piod 29 0>, /* GPIO ETH */
95+
<7 0 &piob 4 0>, /* GPIO */
96+
<8 0 &pioa 3 0>, /* TWD0 EXTx */
97+
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
98+
<10 0 &pioa 5 0>, /* URXD1 EXT3 */
99+
<11 0 &pioa 6 0>, /* UTXD1 EXT3 */
100+
<12 0 &piod 23 0>, /* GPIO */
101+
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
102+
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
103+
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
104+
/* GND */
105+
/* +3.3V */
106+
/* dts-format on */
99107
};
100108

101109
ext3_header: xplained-pro-connector3 {
102110
compatible = "atmel-xplained-pro-header";
103111
#gpio-cells = <2>;
104112
gpio-map-mask = <0xffffffff 0xffffffc0>;
105-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
106-
gpio-map = <0 0 &pioa 17 0>, /* AFE AD0 */
107-
<1 0 &pioc 13 0>, /* AFE AD6 */
108-
<2 0 &piod 28 0>, /* GPIO */
109-
<3 0 &piod 17 0>, /* GPIO */
110-
<4 0 &piod 20 0>, /* PWMH0 */
111-
<5 0 &piod 24 0>, /* PWML0 */
112-
<6 0 &pioe 1 0>, /* GPIO */
113-
<7 0 &piod 26 0>, /* GPIO */
114-
<8 0 &pioa 3 0>, /* TWD0 EXTx */
115-
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
116-
<10 0 &pioa 5 0>, /* URXD1 EXT2 */
117-
<11 0 &pioa 6 0>, /* UTXD1 EXT2 */
118-
<12 0 &piod 30 0>, /* GPIO */
119-
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
120-
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
121-
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
122-
/* GND */
123-
/* +3.3V */
113+
gpio-map-pass-thru = <0 0x3f>;
114+
115+
/* dts-format off */
116+
/* Shared */
117+
gpio-map = <0 0 &pioa 17 0>, /* AFE AD0 */
118+
<1 0 &pioc 13 0>, /* AFE AD6 */
119+
<2 0 &piod 28 0>, /* GPIO */
120+
<3 0 &piod 17 0>, /* GPIO */
121+
<4 0 &piod 20 0>, /* PWMH0 */
122+
<5 0 &piod 24 0>, /* PWML0 */
123+
<6 0 &pioe 1 0>, /* GPIO */
124+
<7 0 &piod 26 0>, /* GPIO */
125+
<8 0 &pioa 3 0>, /* TWD0 EXTx */
126+
<9 0 &pioa 4 0>, /* TWCK0 EXTx */
127+
<10 0 &pioa 5 0>, /* URXD1 EXT2 */
128+
<11 0 &pioa 6 0>, /* UTXD1 EXT2 */
129+
<12 0 &piod 30 0>, /* GPIO */
130+
<13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */
131+
<14 0 &pioa 12 0>, /* SPI(MISO) EXTx */
132+
<15 0 &pioa 14 0>; /* SPI(SCK) EXTx */
133+
/* GND */
134+
/* +3.3V */
135+
/* dts-format on */
124136
};
125137
};
126138

‎boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts‎

Lines changed: 60 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -69,68 +69,84 @@
6969
compatible = "atmel-xplained-header";
7070
#gpio-cells = <2>;
7171
gpio-map-mask = <0xffffffff 0xffffffc0>;
72-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
73-
gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */
74-
<1 0 &pioa 4 0>, /* TWCK0 y */
75-
<2 0 &piob 2 0>, /* URXD1 */
76-
<3 0 &piob 3 0>, /* UTXD1 */
77-
<4 0 &pioa 31 0>, /* SPI(CS) */
78-
<5 0 &pioa 13 0>, /* SPI(MOSI) y */
79-
<6 0 &pioa 12 0>, /* SPI(MISO) y */
80-
<7 0 &pioa 14 0>; /* SPI(SCK) y */
81-
/* GND */
82-
/* +3.3V */
72+
gpio-map-pass-thru = <0 0x3f>;
73+
74+
/* dts-format off */
75+
/* Shared */
76+
gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */
77+
<1 0 &pioa 4 0>, /* TWCK0 y */
78+
<2 0 &piob 2 0>, /* URXD1 */
79+
<3 0 &piob 3 0>, /* UTXD1 */
80+
<4 0 &pioa 31 0>, /* SPI(CS) */
81+
<5 0 &pioa 13 0>, /* SPI(MOSI) y */
82+
<6 0 &pioa 12 0>, /* SPI(MISO) y */
83+
<7 0 &pioa 14 0>; /* SPI(SCK) y */
84+
/* GND */
85+
/* +3.3V */
86+
/* dts-format on */
8387
};
8488

8589
xplained2_header: xplained-connector2 {
8690
compatible = "atmel-xplained-header";
8791
#gpio-cells = <2>;
8892
gpio-map-mask = <0xffffffff 0xffffffc0>;
89-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
90-
gpio-map = <0 0 &pioa 22 0>, /* GPIO */
91-
<1 0 &pioc 12 0>, /* GPIO */
92-
<2 0 &piob 0 0>, /* GPIO */
93-
<3 0 &piob 1 0>, /* GPIO */
94-
<4 0 &pioa 17 0>, /* GPIO */
95-
<5 0 &pioa 21 0>, /* GPIO */
96-
<6 0 &pioc 13 0>, /* GPIO */
97-
<7 0 &pioc 15 0>; /* GPIO */
98-
/* GND */
99-
/* +3.3V */
93+
gpio-map-pass-thru = <0 0x3f>;
94+
95+
/* dts-format off */
96+
/* Shared */
97+
gpio-map = <0 0 &pioa 22 0>, /* GPIO */
98+
<1 0 &pioc 12 0>, /* GPIO */
99+
<2 0 &piob 0 0>, /* GPIO */
100+
<3 0 &piob 1 0>, /* GPIO */
101+
<4 0 &pioa 17 0>, /* GPIO */
102+
<5 0 &pioa 21 0>, /* GPIO */
103+
<6 0 &pioc 13 0>, /* GPIO */
104+
<7 0 &pioc 15 0>; /* GPIO */
105+
/* GND */
106+
/* +3.3V */
107+
/* dts-format on */
100108
};
101109

102110
xplained3_header: xplained-connector3 {
103111
compatible = "atmel-xplained-header";
104112
#gpio-cells = <2>;
105113
gpio-map-mask = <0xffffffff 0xffffffc0>;
106-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
107-
gpio-map = <0 0 &pioa 20 0>, /* GPIO */
108-
<1 0 &pioa 11 0>, /* GPIO */
109-
<2 0 &pioa 23 0>, /* GPIO */
110-
<3 0 &pioa 18 0>, /* GPIO */
111-
<4 0 &pioa 15 0>, /* GPIO */
112-
<5 0 &pioa 16 0>, /* GPIO */
113-
<6 0 &pioa 2 0>, /* GPIO */
114-
<7 0 &pioc 2 0>; /* GPIO */
115-
/* GND */
116-
/* +3.3V */
114+
gpio-map-pass-thru = <0 0x3f>;
115+
116+
/* dts-format off */
117+
/* Shared */
118+
gpio-map = <0 0 &pioa 20 0>, /* GPIO */
119+
<1 0 &pioa 11 0>, /* GPIO */
120+
<2 0 &pioa 23 0>, /* GPIO */
121+
<3 0 &pioa 18 0>, /* GPIO */
122+
<4 0 &pioa 15 0>, /* GPIO */
123+
<5 0 &pioa 16 0>, /* GPIO */
124+
<6 0 &pioa 2 0>, /* GPIO */
125+
<7 0 &pioc 2 0>; /* GPIO */
126+
/* GND */
127+
/* +3.3V */
128+
/* dts-format on */
117129
};
118130

119131
xplained4_header: xplained-connector4 {
120132
compatible = "atmel-xplained-header";
121133
#gpio-cells = <2>;
122134
gpio-map-mask = <0xffffffff 0xffffffc0>;
123-
gpio-map-pass-thru = <0 0x3f>; /* Shared */
124-
gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */
125-
<1 0 &pioa 4 0>, /* TWCK0 y */
126-
<2 0 &piob 2 0>, /* URXD1 */
127-
<3 0 &piob 3 0>, /* UTXD1 */
128-
<4 0 &pioa 30 0>, /* SPI(CS) */
129-
<5 0 &pioa 13 0>, /* SPI(MOSI) y */
130-
<6 0 &pioa 12 0>, /* SPI(MISO) y */
131-
<7 0 &pioa 14 0>; /* SPI(SCK) y */
132-
/* GND */
133-
/* +3.3V */
135+
gpio-map-pass-thru = <0 0x3f>;
136+
137+
/* dts-format off */
138+
/* Shared */
139+
gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */
140+
<1 0 &pioa 4 0>, /* TWCK0 y */
141+
<2 0 &piob 2 0>, /* URXD1 */
142+
<3 0 &piob 3 0>, /* UTXD1 */
143+
<4 0 &pioa 30 0>, /* SPI(CS) */
144+
<5 0 &pioa 13 0>, /* SPI(MOSI) y */
145+
<6 0 &pioa 12 0>, /* SPI(MISO) y */
146+
<7 0 &pioa 14 0>; /* SPI(SCK) y */
147+
/* GND */
148+
/* +3.3V */
149+
/* dts-format on */
134150
};
135151
};
136152

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