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drivers: pinctrl: Support pinctrl with GD32VF103
Change the settings to support pinctrl on the GD32VF103. - Split soc/arm/gigadevice/common/pinctrl_soc.h and put it into include/dt-bindings. - Leave some definitions that can't handle with device tree compiler in pinctrl_soc.h. - Remove dependency to SOC_FAMILY_GD32 because always enabled it if GD32_HAS_AF(IO)_PINMAX was selected. Signed-off-by: TOKITA Hiroshi <[email protected]>
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-177
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6 files changed

+281
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‎drivers/pinctrl/Kconfig.gd32‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,15 @@ DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AFIO := gd,gd32-pinctrl-afio
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config PINCTRL_GD32_AF
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bool "GD32 AF pin controller driver"
9-
depends on SOC_FAMILY_GD32 && GD32_HAS_AF_PINMUX
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depends on GD32_HAS_AF_PINMUX
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default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AF))
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help
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GD32 AF pin controller driver. This driver is used by series using the
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AF pin multiplexing model.
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config PINCTRL_GD32_AFIO
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bool "GD32 AFIO pin controller driver"
17-
depends on SOC_FAMILY_GD32 && GD32_HAS_AFIO_PINMUX
17+
depends on GD32_HAS_AFIO_PINMUX
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default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AFIO))
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help
2020
GD32 AFIO pin controller driver. This driver is used by series using the

‎dts/riscv/gigadevice/gd32vf103.dtsi‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,5 +53,72 @@
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write-block-size = <2>;
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};
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};
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afio: afio@40010000 {
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compatible = "gd,gd32-afio";
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reg = <0x40010000 0x400>;
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rcu-periph-clock = <0x600>;
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status = "okay";
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label = "AFIO";
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};
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pinctrl: pin-controller@40010800 {
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compatible = "gd,gd32-pinctrl-afio";
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reg = <0x40010800 0x1c00>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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label = "PINCTRL";
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gpioa: gpio@40010800 {
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compatible = "gd,gd32-gpio";
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reg = <0x40010800 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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rcu-periph-clock = <0x602>;
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status = "disabled";
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label = "GPIOA";
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};
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gpiob: gpio@40010c00 {
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compatible = "gd,gd32-gpio";
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reg = <0x40010c00 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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rcu-periph-clock = <0x603>;
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status = "disabled";
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label = "GPIOB";
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};
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gpioc: gpio@40011000 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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rcu-periph-clock = <0x604>;
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status = "disabled";
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label = "GPIOC";
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};
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gpiod: gpio@40011400 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011400 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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rcu-periph-clock = <0x605>;
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status = "disabled";
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label = "GPIOD";
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};
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gpioe: gpio@40011800 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011800 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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rcu-periph-clock = <0x606>;
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status = "disabled";
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label = "GPIOE";
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};
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};
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};
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};

‎include/drivers/pinctrl/pinctrl_soc_gd32_common.h‎

Lines changed: 191 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,191 @@
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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* Gigadevice SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#include <devicetree.h>
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#include <zephyr/types.h>
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#ifdef CONFIG_PINCTRL_GD32_AF
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#include <dt-bindings/pinctrl/gd32-af.h>
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#else
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#include <dt-bindings/pinctrl/gd32-afio.h>
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#endif /* CONFIG_PINCTRL_GD32_AF */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/** @brief Type for GD32 pin.
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*
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* Bits (AF model):
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* - 0-12: GD32_PINMUX_AF bit field.
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* - 13-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*
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* Bits (AFIO model):
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* - 0-19: GD32_PINMUX_AFIO bit field.
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* - 20-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*/
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typedef uint32_t pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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(DT_PROP_BY_IDX(node_id, prop, idx) | \
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((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \
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<< GD32_PUPD_POS) | \
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((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \
56+
<< GD32_PUPD_POS) | \
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((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \
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<< GD32_OTYPE_POS) | \
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(DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
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/**
62+
* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
66+
*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
69+
DT_FOREACH_PROP_ELEM, pinmux, \
70+
Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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/**
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* @name GD32 PUPD (values match the ones in the HAL for AF model).
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* @{
77+
*/
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/** No pull-up/down */
80+
#define GD32_PUPD_NONE 0U
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/** Pull-up */
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#define GD32_PUPD_PULLUP 1U
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/** Pull-down */
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#define GD32_PUPD_PULLDOWN 2U
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/** @} */
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/**
89+
* @name GD32 OTYPE (values match the ones in the HAL for AF model).
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* @{
91+
*/
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/** Push-pull */
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#define GD32_OTYPE_PP 0U
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/** Open-drain */
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#define GD32_OTYPE_OD 1U
97+
98+
/** @} */
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/**
101+
* @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
102+
* one for AFIO model).
103+
* @{
104+
*/
105+
106+
#ifdef CONFIG_PINCTRL_GD32_AF
107+
/** Maximum 2MHz */
108+
#define GD32_OSPEED_2MHZ 0U
109+
#ifdef CONFIG_SOC_SERIES_GD32F3X0
110+
/** Maximum 10MHz */
111+
#define GD32_OSPEED_10MHZ 1U
112+
/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 3U
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#else
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/** Maximum 25MHz */
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#define GD32_OSPEED_25MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum 200MHz */
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#define GD32_OSPEED_200MHZ 3U
121+
#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
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#else
123+
/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 0U
125+
/** Maximum 2MHz */
126+
#define GD32_OSPEED_2MHZ 1U
127+
/** Maximum 50MHz */
128+
#define GD32_OSPEED_50MHZ 2U
129+
/** Maximum speed */
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#define GD32_OSPEED_MAX 3U
131+
#endif /* CONFIG_PINCTRL_GD32_AF */
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133+
/** @} */
134+
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/**
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* @name GD32 pin configuration bit field mask and positions.
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* @anchor GD32_PINCFG
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*
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* Fields:
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*
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* - 31..29: Pull-up/down
142+
* - 28: Output type
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* - 27..26: Output speed
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*
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* @{
146+
*/
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/** PUPD field mask. */
149+
#define GD32_PUPD_MSK 0x3U
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/** PUPD field position. */
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#define GD32_PUPD_POS 29U
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/** OTYPE field mask. */
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#define GD32_OTYPE_MSK 0x1U
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/** OTYPE field position. */
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#define GD32_OTYPE_POS 28U
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/** OSPEED field mask. */
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#define GD32_OSPEED_MSK 0x3U
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/** OSPEED field position. */
159+
#define GD32_OSPEED_POS 26U
160+
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/** @} */
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/**
164+
* Obtain PUPD field from pinctrl_soc_pin_t configuration.
165+
*
166+
* @param pincfg pinctrl_soc_pin_t bit field value.
167+
*/
168+
#define GD32_PUPD_GET(pincfg) \
169+
(((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
170+
171+
/**
172+
* Obtain OTYPE field from pinctrl_soc_pin_t configuration.
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*
174+
* @param pincfg pinctrl_soc_pin_t bit field value.
175+
*/
176+
#define GD32_OTYPE_GET(pincfg) \
177+
(((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
178+
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/**
180+
* Obtain OSPEED field from pinctrl_soc_pin_t configuration.
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*
182+
* @param pincfg pinctrl_soc_pin_t bit field value.
183+
*/
184+
#define GD32_OSPEED_GET(pincfg) \
185+
(((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
186+
187+
#ifdef __cplusplus
188+
}
189+
#endif
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191+
#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */

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