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dts: wch: Introduce CH32V203
Introduce CH32V203 SoC Signed-off-by: Camille BAUD <[email protected]>
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‎dts/bindings/cpu/wch,qingke-v4b.yml

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# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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description: WCH QingKe V4B RISC-V MCU
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compatible: "wch,qingke-v4b"
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include: riscv,cpus.yaml

‎dts/riscv/wch/ch32v203/ch32v203.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <mem.h>
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#include <wch/qingke-v4b.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hse-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hsi-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "wch,ch32v20x_30x-pll-clock";
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mul = <15>;
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status = "disabled";
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};
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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flash: flash-controller@40022000 {
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compatible = "wch,ch32v20x_30x-flash-controller";
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reg = <0x40022000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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reg = <0x08000000 DT_SIZE_K(224)>;
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};
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};
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pwr: pwr@40007000 {
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compatible = "wch,pwr";
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reg = <0x40007000 16>;
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};
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pinctrl: pin-controller@40010000 {
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compatible = "wch,20x_30x-afio";
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reg = <0x40010000 16>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@40010800 {
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compatible = "wch,gpio";
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reg = <0x40010800 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
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};
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gpiob: gpio@40010C00 {
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compatible = "wch,gpio";
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reg = <0x40010C00 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
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};
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gpioc: gpio@40011000 {
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compatible = "wch,gpio";
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reg = <0x40011000 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
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};
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gpiod: gpio@40011400 {
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compatible = "wch,gpio";
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reg = <0x40011400 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
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};
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};
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usart1: uart@40013800 {
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compatible = "wch,usart";
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reg = <0x40013800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
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interrupt-parent = <&pfic>;
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interrupts = <53>;
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status = "disabled";
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};
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usart2: uart@40004400 {
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compatible = "wch,usart";
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reg = <0x40004400 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
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interrupt-parent = <&pfic>;
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interrupts = <54>;
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status = "disabled";
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};
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rcc: rcc@40021000 {
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compatible = "wch,rcc";
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reg = <0x40021000 16>;
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#clock-cells = <1>;
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};
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};
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(120)>;
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};

‎dts/riscv/wch/ch32v203/ch32v203c6t.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioc {
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gpio-reserved-ranges = <0 13>;
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};
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&gpiod {
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gpio-reserved-ranges = <2 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(10)>;
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};

‎dts/riscv/wch/ch32v203/ch32v203c6u.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203c6t.dtsi>

‎dts/riscv/wch/ch32v203/ch32v203c8t.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioc {
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gpio-reserved-ranges = <0 13>;
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};
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&gpiod {
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gpio-reserved-ranges = <2 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(20)>;
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};
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/ {
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soc {
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usart3: uart@40004800 {
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compatible = "wch,usart";
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reg = <0x40004800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
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interrupt-parent = <&pfic>;
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interrupts = <55>;
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status = "disabled";
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};
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usart4: uart@40004c00 {
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compatible = "wch,usart";
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reg = <0x40004C00 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
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interrupt-parent = <&pfic>;
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interrupts = <68>;
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status = "disabled";
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};
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};
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};

‎dts/riscv/wch/ch32v203/ch32v203c8u.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203c8t.dtsi>

‎dts/riscv/wch/ch32v203/ch32v203f6p.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioa {
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gpio-reserved-ranges = <8 11>, <15 16>;
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};
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&gpiob {
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gpio-reserved-ranges = <0 1>, <2 8>, <9 16>;
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};
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&gpioc {
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gpio-reserved-ranges = <0 16>;
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};
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&gpiod {
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gpio-reserved-ranges = <2 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(10)>;
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};

‎dts/riscv/wch/ch32v203/ch32v203f8p.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioa {
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gpio-reserved-ranges = <11 13>, <15 16>;
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};
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&gpiob {
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gpio-reserved-ranges = <1 6>, <8 13>;
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};
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&gpioc {
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gpio-reserved-ranges = <0 16>;
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};
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&gpiod {
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gpio-reserved-ranges = <0 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(20)>;
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};

‎dts/riscv/wch/ch32v203/ch32v203f8u.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioa {
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gpio-reserved-ranges = <11 13>, <15 16>;
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};
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&gpiob {
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gpio-reserved-ranges = <2 10>, <12 14>;
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};
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&gpioc {
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gpio-reserved-ranges = <0 16>;
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};
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&gpiod {
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gpio-reserved-ranges = <0 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(20)>;
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};

‎dts/riscv/wch/ch32v203/ch32v203g6u.dtsi

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v203/ch32v203.dtsi>
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&gpioa {
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gpio-reserved-ranges = <8 9>;
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};
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&gpiob {
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gpio-reserved-ranges = <2 3>, <10 16>;
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};
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&gpioc {
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gpio-reserved-ranges = <0 16>;
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};
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&gpiod {
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gpio-reserved-ranges = <2 16>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(10)>;
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};

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