dts: arm: st: add comparator to h7 and g4

adds comparator DTS entities for stm32h7 and stm32g4 series

Signed-off-by: Alexander Kozhinov <[email protected]>

Author: KozhinovAlexander

dts/arm/st/g4/stm32g4.dtsi

@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2021 The Chromium OS Authors
  * Copyright (c) 2019 Richard Osterloh <[email protected]>
+ * Copyright (c) 2024 Alexander Kozhinov <[email protected]>
  * Copyright (c) 2024 STMicroelectronics
  * Copyright (c) 2025 Mario Paja
  *
@@ -698,6 +699,24 @@
 					     STM32_DMA_16BITS)>;
 			status = "disabled";
 		};
+
+		comp1: comparator@40010200 {
+			compatible = "st,stm32g4-comp", "st,stm32-comp";
+			reg = <0x40010200 0x4>;
+			interrupts = <64 0>;
+			st,exti-line = <21>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0)>;
+			status = "disabled";
+		};
+
+		comp2: comparator@40010204 {
+			compatible = "st,stm32g4-comp", "st,stm32-comp";
+			reg = <0x40010204 0x4>;
+			interrupts = <64 0>;
+			st,exti-line = <22>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0)>;
+			status = "disabled";
+		};
 	};
 
 	die_temp: dietemp {

dts/arm/st/h7/stm32h7.dtsi

@@ -1138,6 +1138,24 @@
 				STM32_DMA_16BITS) 0>;
 			status = "disabled";
 		};
+
+		comp1_ch1: comparator@5800380c {
+			compatible = "st,stm32h7-comp", "st,stm32-comp";
+			reg = <0x5800380c 0x200>;
+			interrupts = <137 0>;
+			st,exti-line = <20>;
+			clocks = <&rcc STM32_CLOCK(APB4, 14)>;
+			status = "disabled";
+		};
+
+		comp1_ch2: comparator@58003810 {
+			compatible = "st,stm32h7-comp", "st,stm32-comp";
+			reg = <0x58003810 0x200>;
+			interrupts = <137 0>;
+			st,exti-line = <20>;
+			clocks = <&rcc STM32_CLOCK(APB4, 14)>;
+			status = "disabled";
+		};
 	};
 
 	die_temp: dietemp {