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Nicolas Pitre
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boards: arm: Add unified FVP ARMv9-A board support
New board targets: - fvp_base_revc_2xaem/v9a (basic ARMv9-A single core) - fvp_base_revc_2xaem/v9a/smp (ARMv9-A SMP 4 cores) - fvp_base_revc_2xaem/v9a/smp/ns (ARMv9-A SMP non-secure with TFA) Signed-off-by: Nicolas Pitre <[email protected]>
1 parent e8a5cf4 commit 224742a

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‎boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem‎

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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FVP_BASE_REVC_2XAEM
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select SOC_FVP_V8A
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bool
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select SOC_SERIES_FVP_AEM
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select SOC_FVP_V8A if BOARD_QUALIFIERS = "v8a"
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select SOC_FVP_V8A if BOARD_QUALIFIERS = "v8a/smp"
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select SOC_FVP_V8A if BOARD_QUALIFIERS = "v8a/smp/ns"
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select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a"
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select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a/smp"
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select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a/smp/ns"

‎boards/arm/fvp_base_revc_2xaem/board.cmake‎

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@@ -32,6 +32,24 @@ set(ARMFVP_FLAGS
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-C cache_state_modelled=0
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)
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# Add ARMv9-A specific configuration flags for all ARMv9-A variants
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if(CONFIG_ARMV9_A)
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set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
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# Enable ARMv9.0 extension (includes all ARMv8.x features)
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-C cluster0.has_arm_v9-0=1
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# Enable SVE and SVE2 support (mandatory for ARMv9.0 compliance)
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-C cluster0.has_sve=1
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-C cluster0.sve.has_sve2=1
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-C cluster0.sve.sve2_version=2
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-C cluster0.sve.enable_at_reset=1
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# Enable enhanced PAC and BTI support (ARMv9.0 features)
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-C cluster0.enhanced_pac2_level=3
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-C cluster0.has_enhanced_pac=1
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)
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# Set minimum FVP version known to work with ARMv9.0 features (SVE2, enhanced PAC/BTI)
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set(ARMFVP_MIN_VERSION 11.29.27)
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endif()
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if(CONFIG_BUILD_WITH_TFA)
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set(TFA_PLAT "fvp")
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‎boards/arm/fvp_base_revc_2xaem/board.yml‎

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- name: smp
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variants:
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- name: ns
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- name: v9a
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variants:
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- name: smp
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variants:
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- name: ns

‎boards/arm/fvp_base_revc_2xaem/doc/index.rst‎

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The following board targets are available:
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* ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit)
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* ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit) with Cortex-A53 cores
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* ``fvp_base_revc_2xaem/v8a/smp`` - ARMv8-A SMP (4 cores)
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* ``fvp_base_revc_2xaem/v8a/smp/ns`` - ARMv8-A SMP Non-Secure
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* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) [Future]
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* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) with Cortex-A510 cores
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* ``fvp_base_revc_2xaem/v9a/smp`` - ARMv9-A SMP (4 cores)
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* ``fvp_base_revc_2xaem/v9a/smp/ns`` - ARMv9-A SMP Non-Secure
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Devices
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========
@@ -93,6 +95,14 @@ ARM FVP emulated environment, for example, with the :zephyr:code-sample:`synchro
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This will build an image with the synchronization sample app for ARMv8-A.
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Then you can run it with ``west build -t run``.
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For ARMv9-A variants:
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: fvp_base_revc_2xaem/v9a
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:goals: build
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For SMP variants:
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.. zephyr-app-commands::

‎boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem.dtsi‎

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/*
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* Copyright (c) 2021 Carlo Caione <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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chosen {
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/*
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* The SRAM node is actually located in the
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* DRAM region of the FVP Base RevC 2xAEM.
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*/
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zephyr,sram = &dram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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reg = <0x200>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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reg = <0x300>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@2f000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x2f000000 0x10000>, // GICD
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<0x2f100000 0x200000>; // GICR
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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its: msi-controller@2f020000 {
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compatible = "arm,gic-v3-its";
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reg = <0x2f020000 0x20000>;
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status = "okay";
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};
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};
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v2m_sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x1c010000 0x1000>;
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};
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pwrc: power-controller@1c100000 {
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compatible = "arm,fvp-pwrc";
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reg = <0x1c100000 0x1000>;
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arm,vexpress-sysreg = <&v2m_sysreg>;
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};
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uart0: uart@1c090000 {
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compatible = "arm,pl011";
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reg = <0x1c090000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_5";
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clocks = <&uartclk>;
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};
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uart1: uart@1c0a0000 {
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compatible = "arm,pl011";
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reg = <0x1c0a0000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_6";
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clocks = <&uartclk>;
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};
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uart2: uart@1c0b0000 {
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compatible = "arm,pl011";
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reg = <0x1c0b0000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_7";
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clocks = <&uartclk>;
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};
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uart3: uart@1c0c0000 {
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compatible = "arm,pl011";
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reg = <0x1c0c0000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_8";
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clocks = <&uartclk>;
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};
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ethernet@1a000000 {
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reg = <0x1a000000 0x1000>;
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eth: ethernet {
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compatible = "smsc,lan91c111";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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phy-handle = <&phy>;
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};
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mdio: mdio {
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compatible = "smsc,lan91c111-mdio";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@0 {
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compatible = "ethernet-phy";
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status = "disabled";
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reg = <0>;
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};
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};
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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dram0: memory@88000000 {
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compatible = "mmio-dram";
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reg = <0x88000000 DT_SIZE_K(2048)>;
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};
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};

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