logging: backends: Use CMSIS 6 register defines in SWO initialization

ARM CMSIS 6 has different ITM and TPI register definition comparing
with CMSIS 5. Update the swo initialization to use CMSIS 6 defines.
For the Cortex-M cores which are higher than Cortex-CM7, the LAR
has been removed from ITM.

Signed-off-by: Aaron Ye <[email protected]>

Author: aaronyegx

subsys/logging/backends/log_backend_swo.c

@@ -94,23 +94,25 @@ static void log_backend_swo_init(struct log_backend const *const backend)
 {
 	/* Enable DWT and ITM units */
 	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#if (__CORTEX_M <= 7U)
 	/* Enable access to ITM registers */
 	ITM->LAR  = 0xC5ACCE55;
+#endif
 	/* Disable stimulus ports ITM_STIM0-ITM_STIM31 */
 	ITM->TER  = 0x0;
 	/* Disable ITM */
 	ITM->TCR  = 0x0;
 	/* Select TPIU encoding protocol */
-	TPI->SPPR = IS_ENABLED(CONFIG_LOG_BACKEND_SWO_PROTOCOL_NRZ) ? 2 : 1;
+	TPIU->SPPR = IS_ENABLED(CONFIG_LOG_BACKEND_SWO_PROTOCOL_NRZ) ? 2 : 1;
 	/* Set SWO baud rate prescaler value: SWO_clk = ref_clock/(ACPR + 1) */
-	TPI->ACPR = SWO_FREQ_DIV - 1;
+	TPIU->ACPR = SWO_FREQ_DIV - 1;
 	/* Enable unprivileged access to ITM stimulus ports */
 	ITM->TPR  = 0x0;
 	/* Configure Debug Watchpoint and Trace */
 	DWT->CTRL &= (DWT_CTRL_POSTPRESET_Msk | DWT_CTRL_POSTINIT_Msk | DWT_CTRL_CYCCNTENA_Msk);
 	DWT->CTRL |= (DWT_CTRL_POSTPRESET_Msk | DWT_CTRL_POSTINIT_Msk);
 	/* Configure Formatter and Flush Control Register */
-	TPI->FFCR = 0x00000100;
+	TPIU->FFCR = 0x00000100;
 	/* Enable ITM, set TraceBusID=1, no local timestamp generation */
 	ITM->TCR  = 0x0001000D;
 	/* Enable stimulus port used by the logger */