[WIP] arch: riscv: smp: add PLIC-based IPI implementation

Add PLIC-based IPI implementation.

Signed-off-by: Yong Cong Sin <[email protected]>

Author: ycsin

arch/riscv/Kconfig

@@ -41,6 +41,7 @@ choice RISCV_SMP_IPI_IMPL
 	prompt "RISC-V SMP IPI implementation"
 	depends on SMP
 	default RISCV_SMP_IPI_CLINT if DT_HAS_SIFIVE_CLINT0_ENABLED
+	default RISCV_SMP_IPI_PLIC if PLIC_SUPPORTS_SOFT_INTERRUPT && PLIC_IRQ_AFFINITY
 	default RISCV_SMP_IPI_CUSTOM
 
 config RISCV_SMP_IPI_CLINT
@@ -49,6 +50,13 @@ config RISCV_SMP_IPI_CLINT
 	help
 	  Use CLINT-based IPI implementation.
 
+config RISCV_SMP_IPI_PLIC
+	bool "PLIC-based IPI"
+	depends on PLIC_SUPPORTS_SOFT_INTERRUPT
+	depends on PLIC_IRQ_AFFINITY
+	help
+	  Use PLIC-based IPI implementation.
+
 config RISCV_SMP_IPI_CUSTOM
 	bool "Custom IPI implementation"
 	help

arch/riscv/core/ipi_impl.h

@@ -11,6 +11,8 @@ void z_riscv_sched_ipi_handler(unsigned int cpu_id);
 
 #ifdef CONFIG_RISCV_SMP_IPI_CLINT
 #include "ipi_clint.h"
+#elif defined(CONFIG_RISCV_SMP_IPI_PLIC)
+#include "ipi_plic.h"
 #else /* CONFIG_RISCV_SMP_IPI_CUSTOM */
 inline void z_riscv_ipi_send(unsigned int cpu);
 inline void z_riscv_ipi_clear(unsigned int cpu);

arch/riscv/core/ipi_plic.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_
+#define ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
+#include <zephyr/irq_multilevel.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+
+#define DT_DRV_COMPAT zephyr_ipi_plic
+
+#define IPI_PLIC_IRQS(n, _) DT_INST_IRQN_BY_IDX(0, n)
+
+/* Should get this from the devicetree, placeholder now */
+static const uint32_t ipi_irqs[CONFIG_MP_MAX_NUM_CPUS] = {
+	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, IPI_PLIC_IRQS, (,)),
+};
+
+static ALWAYS_INLINE void z_riscv_ipi_send(unsigned int cpu)
+{
+	riscv_plic_irq_set_pending(ipi_irqs[cpu]);
+}
+
+static ALWAYS_INLINE void z_riscv_ipi_clear(unsigned int cpu)
+{
+	ARG_UNUSED(cpu);
+	/* IRQ will be cleared by PLIC */
+}
+
+static void sched_ipi_handler(const void *arg)
+{
+	unsigned int cpu_id = POINTER_TO_UINT(arg);
+
+	z_riscv_sched_ipi_handler(cpu_id);
+}
+
+#define IPI_PLIC_IRQ_CONNECT(n, _)                                                                 \
+	IRQ_CONNECT(DT_INST_IRQN_BY_IDX(0, n), 1, sched_ipi_handler, UINT_TO_POINTER(n), 0);       \
+	irq_enable(n);                                                                             \
+	riscv_plic_irq_set_affinity(n, BIT(n))
+
+int arch_smp_init(void)
+{
+	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, IPI_PLIC_IRQ_CONNECT, (;));
+
+	return 0;
+}
+
+#endif /* ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_ */

boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts

@@ -140,6 +140,19 @@
 			zephyr,code = <INPUT_KEY_6>;
 		};
 	};
+
+	ipi_plic: ipi_plic {
+		compatible = "zephyr,ipi-plic";
+		interrupt-parent = <&plic_sw>;
+		interrupts = <1 1>,  /* CPU 0 */
+			     <2 1>,  /* CPU 1 */
+			     <3 1>,  /* CPU 2 */
+			     <4 1>,  /* CPU 3 */
+			     <5 1>,  /* CPU 4 */
+			     <6 1>,  /* CPU 5 */
+			     <7 1>,  /* CPU 6 */
+			     <8 1>;  /* CPU 7 */
+	};
 };
 
 &l2_cache {

dts/bindings/misc/zephyr,ipi-plic.yaml

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: IPI PLIC pseudo device
+
+compatible: "zephyr,ipi-plic"
+
+include: [base.yaml]
+
+properties:
+  interrupt-parent:
+    required: true
+
+  interrupts:
+    required: true