boards: arm: Add unified FVP ARMv9-A board support

New board Targets:
- fvp_base_revc_2xaem/v9a (basic ARMv9-A single core)
- fvp_base_revc_2xaem/v9a/smp (ARMv9-A SMP 4 cores)
- fvp_base_revc_2xaem/v9a/smp/ns (ARMv9-A SMP non-secure with TFA)

Signed-off-by: Nicolas Pitre <[email protected]>

Author: Nicolas Pitre

boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem

@@ -2,4 +2,27 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_FVP_BASE_REVC_2XAEM
+	bool
+	select SOC_SERIES_FVP_AEM
+
+# Board variant symbols - these should be automatically generated by the build system
+# but we need to define them explicitly for the SOC selection logic to work
+config BOARD_FVP_BASE_REVC_2XAEM_V8A
+	bool
+	default y if BOARD_QUALIFIERS = "v8a"
 	select SOC_FVP_V8A
+
+config BOARD_FVP_BASE_REVC_2XAEM_V8A_SMP
+	bool
+	default y if BOARD_QUALIFIERS = "v8a/smp" || BOARD_QUALIFIERS = "v8a/smp/ns"
+	select BOARD_FVP_BASE_REVC_2XAEM_V8A
+
+config BOARD_FVP_BASE_REVC_2XAEM_V9A
+	bool
+	default y if BOARD_QUALIFIERS = "v9a"
+	select SOC_FVP_V9A
+
+config BOARD_FVP_BASE_REVC_2XAEM_V9A_SMP
+	bool
+	default y if BOARD_QUALIFIERS = "v9a/smp" || BOARD_QUALIFIERS = "v9a/smp/ns"
+	select BOARD_FVP_BASE_REVC_2XAEM_V9A

boards/arm/fvp_base_revc_2xaem/board.cmake

@@ -32,6 +32,24 @@ set(ARMFVP_FLAGS
   -C cache_state_modelled=0
   )
 
+# Add ARMv9-A specific configuration flags for all ARMv9-A variants
+if(CONFIG_ARMV9_A)
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+    # Enable ARMv9.0 extension (includes all ARMv8.x features)
+    -C cluster0.has_arm_v9-0=1
+    # Enable SVE and SVE2 support (mandatory for ARMv9.0 compliance)
+    -C cluster0.has_sve=1
+    -C cluster0.sve.has_sve2=1
+    -C cluster0.sve.sve2_version=2
+    -C cluster0.sve.enable_at_reset=1
+    # Enable enhanced PAC and BTI support (ARMv9.0 features)
+    -C cluster0.enhanced_pac2_level=3
+    -C cluster0.has_enhanced_pac=1
+    )
+  # Set minimum FVP version known to work with ARMv9.0 features (SVE2, enhanced PAC/BTI)
+  set(ARMFVP_MIN_VERSION 11.29.27)
+endif()
+
 if(CONFIG_BUILD_WITH_TFA)
   set(TFA_PLAT "fvp")
 

boards/arm/fvp_base_revc_2xaem/board.yml

@@ -8,3 +8,8 @@ board:
     - name: smp
       variants:
       - name: ns
+  - name: v9a
+    variants:
+    - name: smp
+      variants:
+      - name: ns

boards/arm/fvp_base_revc_2xaem/doc/index.rst

@@ -43,10 +43,12 @@ Board Variants
 
 This board configuration supports multiple architecture variants:
 
-* ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit)
+* ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit) with Cortex-A53 cores
 * ``fvp_base_revc_2xaem/v8a/smp`` - ARMv8-A SMP (4 cores)
 * ``fvp_base_revc_2xaem/v8a/smp/ns`` - ARMv8-A SMP Non-Secure
-* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) [Future]
+* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) with Cortex-A510 cores
+* ``fvp_base_revc_2xaem/v9a/smp`` - ARMv9-A SMP (4 cores)
+* ``fvp_base_revc_2xaem/v9a/smp/ns`` - ARMv9-A SMP Non-Secure
 
 Devices
 ========
@@ -93,6 +95,14 @@ ARM FVP emulated environment, for example, with the :zephyr:code-sample:`synchro
 This will build an image with the synchronization sample app for ARMv8-A.
 Then you can run it with ``west build -t run``.
 
+For ARMv9-A variants:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: fvp_base_revc_2xaem/v9a
+   :goals: build
+
 For SMP variants:
 
 .. zephyr-app-commands::

boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem.dtsi

@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	chosen {
+		/*
+		 * The SRAM node is actually located in the
+		 * DRAM region of the FVP Base RevC 2xAEM.
+		 */
+		zephyr,sram = &dram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			reg = <0x100>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			reg = <0x200>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			reg = <0x300>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+	};
+
+	uartclk: apb-pclk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@2f000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x2f000000 0x10000>, // GICD
+			      <0x2f100000 0x200000>; // GICR
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			its: msi-controller@2f020000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x2f020000 0x20000>;
+				status = "okay";
+			};
+		};
+
+		uart0: uart@1c090000 {
+			compatible = "arm,pl011";
+			reg = <0x1c090000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_5";
+			clocks = <&uartclk>;
+		};
+
+		uart1: uart@1c0a0000 {
+			compatible = "arm,pl011";
+			reg = <0x1c0a0000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_6";
+			clocks = <&uartclk>;
+		};
+
+		uart2: uart@1c0b0000 {
+			compatible = "arm,pl011";
+			reg = <0x1c0b0000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_7";
+			clocks = <&uartclk>;
+		};
+
+		uart3: uart@1c0c0000 {
+			compatible = "arm,pl011";
+			reg = <0x1c0c0000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_8";
+			clocks = <&uartclk>;
+		};
+
+		ethernet@1a000000 {
+			reg = <0x1a000000 0x1000>;
+
+			eth: ethernet {
+				compatible = "smsc,lan91c111";
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+
+				phy-handle = <&phy>;
+			};
+
+			mdio: mdio {
+				compatible = "smsc,lan91c111-mdio";
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				phy: ethernet-phy@0 {
+					compatible = "ethernet-phy";
+					status = "disabled";
+					reg = <0>;
+				};
+			};
+		};
+
+		flash0: flash@0 {
+			compatible = "soc-nv-flash";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		dram0: memory@88000000 {
+			compatible = "mmio-dram";
+			reg = <0x88000000 DT_SIZE_K(2048)>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};