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drivers: mipi_dsi: add support for MIPI DSI driver on Renesas RA family
First commit to add support for MIPI DSI driver on Renesas RA Signed-off-by: The Nguyen <[email protected]>
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‎drivers/mipi_dsi/CMakeLists.txt

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@@ -3,3 +3,4 @@ zephyr_sources_ifdef(CONFIG_MIPI_DSI_MCUX dsi_mcux.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_MCUX_2L dsi_mcux_2l.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_STM32 dsi_stm32.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_TEST dsi_test.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_RENESAS_RA dsi_renesas_ra.c)

‎drivers/mipi_dsi/Kconfig

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@@ -24,5 +24,6 @@ config MIPI_DSI_INIT_PRIORITY
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source "drivers/mipi_dsi/Kconfig.mcux"
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source "drivers/mipi_dsi/Kconfig.stm32"
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source "drivers/mipi_dsi/Kconfig.test"
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source "drivers/mipi_dsi/Kconfig.renesas_ra"
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endif

‎drivers/mipi_dsi/Kconfig.renesas_ra

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@@ -0,0 +1,12 @@
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# Renesas RA Family
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config MIPI_DSI_RENESAS_RA
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bool "Renesas RA MIPI-DSI Host Controller"
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default y
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depends on DT_HAS_RENESAS_RA_MIPI_DSI_ENABLED
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select USE_RA_FSP_MIPI_DSI
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help
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Renesas RA MIPI DSI controller driver

‎drivers/mipi_dsi/dsi_renesas_ra.c

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_mipi_dsi
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/mipi_dsi.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include "r_mipi_dsi.h"
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#include "r_mipi_phy.h"
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LOG_MODULE_REGISTER(dsi_renesas_ra, CONFIG_MIPI_DSI_LOG_LEVEL);
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/* MIPI PHY Macros */
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#define MIPI_PHY_CLKSTPT (1183)
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#define MIPI_PHY_CLKBFHT (11)
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#define MIPI_PHY_CLKKPT (26)
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#define MIPI_PHY_GOLPBKT (40)
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#define MIPI_PHY_TINIT (71999)
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#define MIPI_PHY_TCLKPREP (8)
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#define MIPI_PHY_THSPREP (5)
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#define MIPI_PHY_TCLKTRAIL (7)
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#define MIPI_PHY_TCLKPOST (19)
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#define MIPI_PHY_TCLKPRE (1)
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#define MIPI_PHY_TCLKZERO (27)
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#define MIPI_PHY_THSEXIT (11)
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#define MIPI_PHY_THSTRAIL (8)
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#define MIPI_PHY_THSZERO (19)
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#define MIPI_PHY_TLPEXIT (7)
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#define LP_DIVISOR (4)
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#define PLL_MUL_SETTING (49)
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#define VIDEO_MODE_DELAY (186)
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#define ULPS_WAKEUP_PERIOD (97)
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struct mipi_dsi_renesas_ra_config {
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const struct device *clock_dev;
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struct clock_control_ra_subsys_cfg clock_dsi_subsys;
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void (*irq_configure)(void);
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};
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struct mipi_dsi_renesas_ra_data {
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mipi_dsi_instance_ctrl_t mipi_dsi_ctrl;
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mipi_dsi_cfg_t mipi_dsi_cfg;
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volatile bool message_sent;
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volatile bool fatal_error;
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};
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void mipi_dsi_seq0(void);
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void mipi_dsi_ferr(void);
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void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args);
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typedef struct {
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unsigned char size;
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unsigned char buffer[256];
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mipi_dsi_cmd_id_t cmd_id;
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mipi_dsi_cmd_flag_t flags;
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} lcd_table_setting_t;
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void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args)
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{
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const struct device *dev = (struct device *)p_args->p_context;
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struct mipi_dsi_renesas_ra_data *data = dev->data;
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switch (p_args->event) {
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case MIPI_DSI_EVENT_SEQUENCE_0: {
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if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status) {
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data->message_sent = true;
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}
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break;
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}
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case MIPI_DSI_EVENT_FATAL: {
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data->fatal_error = true;
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break;
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}
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default: {
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break;
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}
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}
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}
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static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
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const struct mipi_dsi_device *mdev)
92+
{
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struct mipi_dsi_renesas_ra_data *data = dev->data;
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mipi_dsi_cfg_t cfg = data->mipi_dsi_cfg;
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int ret;
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if (!(mdev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
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LOG_ERR("DSI host supports video mode only!");
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return -ENOTSUP;
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}
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cfg.virtual_channel_id = channel;
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cfg.num_lanes = mdev->data_lanes;
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if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB888) {
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cfg.data_type = MIPI_DSI_VIDEO_DATA_24RGB_PIXEL_STREAM;
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} else if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB565) {
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cfg.data_type = MIPI_DSI_VIDEO_DATA_16RGB_PIXEL_STREAM;
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}
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cfg.horizontal_active_lines = mdev->timings.hactive;
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cfg.horizontal_front_porch = mdev->timings.hfp;
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cfg.horizontal_back_porch = mdev->timings.hbp;
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cfg.horizontal_sync_lines = mdev->timings.hsync;
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cfg.vertical_active_lines = mdev->timings.vactive;
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cfg.vertical_front_porch = mdev->timings.vfp;
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cfg.vertical_back_porch = mdev->timings.vbp;
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cfg.vertical_sync_lines = mdev->timings.vsync;
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ret = R_MIPI_DSI_Open(&data->mipi_dsi_ctrl, &cfg);
119+
if (ret) {
120+
LOG_ERR("Open DSI failed (%d)", ret);
121+
return -EIO;
122+
}
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ret = R_MIPI_DSI_Start(&data->mipi_dsi_ctrl);
125+
if (ret) {
126+
LOG_ERR("Start DSI host failed! (%d)", ret);
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return -EIO;
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}
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return 0;
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}
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static ssize_t mipi_dsi_renesas_ra_transfer(const struct device *dev, uint8_t channel,
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struct mipi_dsi_msg *msg)
135+
{
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struct mipi_dsi_renesas_ra_data *data = dev->data;
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ssize_t len;
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int ret;
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uint8_t combined_tx_buffer[msg->tx_len + 1];
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combined_tx_buffer[0] = msg->cmd;
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memcpy(&combined_tx_buffer[1], msg->tx_buf, msg->tx_len);
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mipi_dsi_cmd_t fsp_msg = {
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.channel = channel,
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.cmd_id = msg->type,
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.flags = MIPI_DSI_CMD_FLAG_LOW_POWER,
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.tx_len = msg->tx_len + 1,
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.p_tx_buffer = combined_tx_buffer,
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};
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data->message_sent = false;
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data->fatal_error = false;
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switch (msg->type) {
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case MIPI_DSI_DCS_READ:
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LOG_ERR("DCS Read not yet implemented or used");
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return -ENOTSUP;
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_DCS_LONG_WRITE:
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ret = R_MIPI_DSI_Command(&data->mipi_dsi_ctrl, &fsp_msg);
162+
if (ret) {
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LOG_ERR("DSI write fail: err: (%d)", ret);
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return -EIO;
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}
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while (!(data->message_sent)) {
167+
if (data->fatal_error) {
168+
LOG_ERR("fatal error");
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return -EIO;
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}
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}
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len = msg->tx_len;
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break;
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default:
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LOG_ERR("Unsupported message type (%d)", msg->type);
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return -ENOTSUP;
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}
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return len;
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}
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static DEVICE_API(mipi_dsi, mipi_dsi_api) = {
183+
.attach = mipi_dsi_renesas_ra_attach,
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.transfer = mipi_dsi_renesas_ra_transfer,
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};
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static int mipi_dsi_renesas_ra_init(const struct device *dev)
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{
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const struct mipi_dsi_renesas_ra_config *config = dev->config;
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struct mipi_dsi_renesas_ra_data *data = dev->data;
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int ret;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev,
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(clock_control_subsys_t)&config->clock_dsi_subsys);
200+
if (ret) {
201+
LOG_ERR("Enable DSI peripheral clock failed! (%d)", ret);
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return ret;
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}
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config->irq_configure();
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data->mipi_dsi_cfg.p_context = dev;
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return 0;
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}
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#define IRQ_CONFIGURE_FUNC(id) \
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static void mipi_dsi_ra_configure_func_##id(void) \
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{ \
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R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, sq0, irq)] = ELC_EVENT_MIPIDSI_SEQ0; \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, sq0, irq), \
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DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0, \
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DEVICE_DT_INST_GET(id), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(id, sq0, irq)); \
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R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, ferr, irq)] = ELC_EVENT_MIPIDSI_FERR; \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, ferr, irq), \
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DT_INST_IRQ_BY_NAME(id, ferr, priority), mipi_dsi_ferr, \
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DEVICE_DT_INST_GET(id), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(id, ferr, irq)); \
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}
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#define IRQ_CONFIGURE_DEFINE(id) .irq_configure = mipi_dsi_ra_configure_func_##id
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#define RENESAS_MIPI_DSI_DEVICE(id) \
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IRQ_CONFIGURE_FUNC(id) \
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mipi_phy_ctrl_t mipi_phy_##id##_ctrl; \
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static const mipi_phy_timing_t mipi_phy_##id##_timing = { \
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.t_init = 0x3FFFF & (uint32_t)MIPI_PHY_TINIT, \
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.t_clk_prep = (uint8_t)MIPI_PHY_TCLKPREP, \
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.t_hs_prep = (uint8_t)MIPI_PHY_THSPREP, \
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.dphytim4_b.t_clk_trail = (uint32_t)MIPI_PHY_TCLKTRAIL, \
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.dphytim4_b.t_clk_post = (uint32_t)MIPI_PHY_TCLKPOST, \
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.dphytim4_b.t_clk_pre = (uint32_t)MIPI_PHY_TCLKPRE, \
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.dphytim4_b.t_clk_zero = (uint32_t)MIPI_PHY_TCLKZERO, \
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.dphytim5_b.t_hs_exit = (uint32_t)MIPI_PHY_THSEXIT, \
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.dphytim5_b.t_hs_trail = (uint32_t)MIPI_PHY_THSTRAIL, \
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.dphytim5_b.t_hs_zero = (uint32_t)MIPI_PHY_THSZERO, \
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.t_lp_exit = (uint32_t)MIPI_PHY_TLPEXIT, \
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}; \
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static const mipi_phy_cfg_t mipi_phy_##id##_cfg = { \
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.pll_settings = {.div = 0, .mul_int = PLL_MUL_SETTING, .mul_frac = 0}, \
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.lp_divisor = LP_DIVISOR, \
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.p_timing = &mipi_phy_##id##_timing, \
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}; \
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static const mipi_phy_instance_t mipi_phy##id = { \
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.p_ctrl = &mipi_phy_##id##_ctrl, \
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.p_cfg = &mipi_phy_##id##_cfg, \
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.p_api = &g_mipi_phy, \
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}; \
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static const mipi_dsi_extended_cfg_t mipi_dsi_##id##_extended_cfg = { \
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.dsi_seq0.ipl = DT_INST_IRQ_BY_NAME(id, sq0, priority), \
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.dsi_seq0.irq = DT_INST_IRQ_BY_NAME(id, sq0, irq), \
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.dsi_seq1.ipl = DT_INST_IRQ_BY_NAME(id, sq1, priority), \
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.dsi_seq1.irq = DT_INST_IRQ_BY_NAME(id, sq1, irq), \
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.dsi_vin1.ipl = DT_INST_IRQ_BY_NAME(id, vm, priority), \
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.dsi_vin1.irq = DT_INST_IRQ_BY_NAME(id, vm, irq), \
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.dsi_rcv.ipl = DT_INST_IRQ_BY_NAME(id, rcv, priority), \
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.dsi_rcv.irq = DT_INST_IRQ_BY_NAME(id, rcv, irq), \
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.dsi_ferr.ipl = DT_INST_IRQ_BY_NAME(id, ferr, priority), \
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.dsi_ferr.irq = DT_INST_IRQ_BY_NAME(id, ferr, irq), \
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.dsi_ppi.ipl = DT_INST_IRQ_BY_NAME(id, ppi, priority), \
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.dsi_ppi.irq = DT_INST_IRQ_BY_NAME(id, ppi, irq), \
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.dsi_rxie = R_DSILINK_RXIER_BTAREND_Msk | R_DSILINK_RXIER_LRXHTO_Msk | \
268+
R_DSILINK_RXIER_TATO_Msk | R_DSILINK_RXIER_RXRESP_Msk | \
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R_DSILINK_RXIER_RXEOTP_Msk | R_DSILINK_RXIER_RXTE_Msk | \
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R_DSILINK_RXIER_RXACK_Msk | R_DSILINK_RXIER_EXTEDET_Msk | \
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R_DSILINK_RXIER_MLFERR_Msk | R_DSILINK_RXIER_ECCERRM_Msk | \
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R_DSILINK_RXIER_UNEXERR_Msk | R_DSILINK_RXIER_WCERR_Msk | \
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R_DSILINK_RXIER_CRCERR_Msk | R_DSILINK_RXIER_IBERR_Msk | \
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R_DSILINK_RXIER_RXOVFERR_Msk | R_DSILINK_RXIER_PRTOERR_Msk | \
275+
R_DSILINK_RXIER_NORESERR_Msk | R_DSILINK_RXIER_RSIZEERR_Msk | \
276+
R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk | 0x0, \
277+
.dsi_ferrie = R_DSILINK_FERRIER_HTXTO_Msk | R_DSILINK_FERRIER_LRXHTO_Msk | \
278+
R_DSILINK_FERRIER_TATO_Msk | R_DSILINK_FERRIER_ESCENT_Msk | \
279+
R_DSILINK_FERRIER_SYNCESC_Msk | R_DSILINK_FERRIER_CTRL_Msk | \
280+
R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk | 0x0, \
281+
.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk | 0x0, \
282+
.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk | 0x0, \
283+
.dsi_sqch0ie = R_DSILINK_SQCH0IER_AACTFIN_Msk | R_DSILINK_SQCH0IER_ADESFIN_Msk | \
284+
R_DSILINK_SQCH0IER_TXIBERR_Msk | R_DSILINK_SQCH0IER_RXFERR_Msk | \
285+
R_DSILINK_SQCH0IER_RXFAIL_Msk | R_DSILINK_SQCH0IER_RXPFAIL_Msk | \
286+
R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk | \
287+
0x0, \
288+
.dsi_sqch1ie = R_DSILINK_SQCH1IER_AACTFIN_Msk | R_DSILINK_SQCH1IER_ADESFIN_Msk | \
289+
R_DSILINK_SQCH1IER_SIZEERR_Msk | R_DSILINK_SQCH1IER_TXIBERR_Msk | \
290+
R_DSILINK_SQCH1IER_RXFERR_Msk | R_DSILINK_SQCH1IER_RXFAIL_Msk | \
291+
R_DSILINK_SQCH1IER_RXPFAIL_Msk | R_DSILINK_SQCH1IER_RXCORERR_Msk | \
292+
R_DSILINK_SQCH1IER_RXAKE_Msk | 0x0, \
293+
}; \
294+
static const mipi_dsi_timing_t mipi_dsi_##id##_timing = { \
295+
.clock_stop_time = MIPI_PHY_CLKSTPT, \
296+
.clock_beforehand_time = MIPI_PHY_CLKBFHT, \
297+
.clock_keep_time = MIPI_PHY_CLKKPT, \
298+
.go_lp_and_back = MIPI_PHY_GOLPBKT, \
299+
}; \
300+
static const struct mipi_dsi_renesas_ra_config ra_config_##id = { \
301+
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
302+
IRQ_CONFIGURE_DEFINE(id), \
303+
.clock_dsi_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp), \
304+
.stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)}}; \
305+
static struct mipi_dsi_renesas_ra_data ra_data_##id = { \
306+
.mipi_dsi_cfg = \
307+
{ \
308+
.p_mipi_phy_instance = &mipi_phy##id, \
309+
.p_timing = &mipi_dsi_##id##_timing, \
310+
.sync_pulse = (0), \
311+
.data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24, \
312+
.vertical_sync_polarity = 1, \
313+
.horizontal_sync_polarity = 1, \
314+
.video_mode_delay = VIDEO_MODE_DELAY, \
315+
.hsa_no_lp = ((0x0) & R_DSILINK_VMSET0R_HSANOLP_Msk), \
316+
.hbp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HBPNOLP_Msk), \
317+
.hfp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HFPNOLP_Msk), \
318+
.num_lanes = \
319+
DT_PROP_BY_IDX(DT_NODELABEL(ili9806e), data_lanes, 0), \
320+
.ulps_wakeup_period = ULPS_WAKEUP_PERIOD, \
321+
.continuous_clock = (1), \
322+
.hs_tx_timeout = 0, \
323+
.lp_rx_timeout = 0, \
324+
.turnaround_timeout = 0, \
325+
.bta_timeout = 0, \
326+
.lprw_timeout = (0 << R_DSILINK_PRESPTOLPSETR_LPRTO_Pos) | 0, \
327+
.hsrw_timeout = (0 << R_DSILINK_PRESPTOHSSETR_HSRTO_Pos) | 0, \
328+
.max_return_packet_size = 1, \
329+
.ecc_enable = (1), \
330+
.crc_check_mask = (mipi_dsi_vc_t)(0x0), \
331+
.scramble_enable = (0), \
332+
.tearing_detect = (0), \
333+
.eotp_enable = (1), \
334+
.p_extend = &mipi_dsi_##id##_extended_cfg, \
335+
.p_callback = mipi_dsi_callback, \
336+
.p_context = NULL, \
337+
}, \
338+
}; \
339+
DEVICE_DT_INST_DEFINE(id, &mipi_dsi_renesas_ra_init, NULL, &ra_data_##id, &ra_config_##id, \
340+
POST_KERNEL, CONFIG_MIPI_DSI_INIT_PRIORITY, &mipi_dsi_api);
341+
342+
DT_INST_FOREACH_STATUS_OKAY(RENESAS_MIPI_DSI_DEVICE)

‎dts/bindings/gpio/renesas,mipi-header.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
5+
GPIO pins exposed on Renesas MIPI lcd display headers.
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The Renesas MIPI lcd display layout provides 2 columns of 13 pins headers
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This binding provides a mapping for the default 26 pins as depicted below:
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1 GND IIC_SDA 14
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2 GND DISP_BLEN 15
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3 MIPI_DL0_P IIC_SCL 16
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4 MIPI_DL1_P DISP_INT 17
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5 MIPI_DL0_N DISP_RST 18
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6 MIPI_DL1_N GND 19
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7 GND GND 20
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8 GND 1V8 21
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9 MIPI_CL_P 1V8 22
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10 GND 3V3 23
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11 MIPI_CL_N 3V3 24
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12 GND 5V0 25
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13 GND 5V0 26
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compatible: "renesas,ra-gpio-mipi-header"
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include: [gpio-nexus.yaml, base.yaml]

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