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dts/soc: sophgo: Add SOPHGO CV1800B
CV180x is a series of RV64 SoCs developed by SOPHGO (formerly CVITEK), based on T-Head C906 CPU. Co-authored-by: honglin leng <[email protected]> Signed-off-by: Chen Xingyu <[email protected]>
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‎dts/riscv/sophgo/cv180x.dtsi

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/*
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* Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <sophgo/cv18xx-c906-common.dtsi>
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/ {
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soc {
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compatible = "sophgo,cv180x", "simple-bus";
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gpioa: gpio@3020000 {
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compatible = "snps,designware-gpio";
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reg = <0x3020000 DT_SIZE_K(4)>;
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interrupts = <41 1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@3021000 {
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compatible = "snps,designware-gpio";
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reg = <0x3021000 DT_SIZE_K(4)>;
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interrupts = <42 1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@3022000 {
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compatible = "snps,designware-gpio";
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reg = <0x3022000 DT_SIZE_K(4)>;
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interrupts = <43 1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@3023000 {
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compatible = "snps,designware-gpio";
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reg = <0x3023000 DT_SIZE_K(4)>;
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interrupts = <44 1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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uart0: uart@4140000 {
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compatible = "ns16550";
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reg = <0x4140000 DT_SIZE_K(64)>;
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interrupts = <30 1>;
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reg-shift = <2>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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uart1: uart@4150000 {
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compatible = "ns16550";
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reg = <0x4150000 DT_SIZE_K(64)>;
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interrupts = <31 1>;
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reg-shift = <2>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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uart2: uart@4160000 {
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compatible = "ns16550";
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reg = <0x4160000 DT_SIZE_K(64)>;
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/* interrupt is not supported */
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reg-shift = <2>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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uart3: uart@4170000 {
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compatible = "ns16550";
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reg = <0x4170000 DT_SIZE_K(64)>;
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/* interrupt is not supported */
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reg-shift = <2>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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uart4: uart@41c0000 {
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compatible = "ns16550";
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reg = <0x41c0000 DT_SIZE_K(64)>;
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/* interrupt is not supported */
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reg-shift = <2>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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};
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};

‎dts/riscv/sophgo/cv18xx-c906-common.dtsi

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/*
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* Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "thead,c906";
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reg = <0>;
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clock-frequency = <DT_FREQ_M(700)>;
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mmu-type = "riscv,none";
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riscv,isa = "rv64imafdc_zicsr_zifencei";
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hlic: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&plic0>;
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plic0: interrupt-controller@70000000 {
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compatible = "sifive,plic-1.0.0";
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reg = <0x70000000 0x4000000>;
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interrupts-extended = <&hlic 11>;
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interrupt-controller;
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riscv,max-priority = <7>;
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riscv,ndev = <101>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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};
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systick: systick@74000000 {
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compatible = "riscv,machine-timer";
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reg = <0x74004000 0x8>;
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reg-names = "mtimecmp";
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interrupts-extended = <&hlic 7>;
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mtime-is-csr;
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mtimecmp-is-32bits;
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};
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};
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};

‎soc/sophgo/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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add_subdirectory(${SOC_SERIES})

‎soc/sophgo/Kconfig

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_SOPHGO
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rsource "*/Kconfig"
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endif # SOC_FAMILY_SOPHGO

‎soc/sophgo/Kconfig.defconfig

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_SOPHGO
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_SOPHGO

‎soc/sophgo/Kconfig.soc

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_SOPHGO
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bool
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config SOC_FAMILY
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default "sophgo" if SOC_FAMILY_SOPHGO
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rsource "*/Kconfig.soc"

‎soc/sophgo/common/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)

‎soc/sophgo/cv180x/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

‎soc/sophgo/cv180x/Kconfig

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_CV180X
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select 64BIT
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_ISA_RV64I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_F
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select RISCV_ISA_EXT_D
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
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select INCLUDE_RESET_VECTOR
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select ATOMIC_OPERATIONS_C

‎soc/sophgo/cv180x/Kconfig.defconfig

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_CV180X
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000
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config NUM_IRQS
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int
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default 128
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_HAS_PLIC
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default y
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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endif # SOC_SERIES_CV180X

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