soc: esp32c3: update startup code to map IROM and DROM segments

This change updates startup code to setup MMU mappings

Signed-off-by: Sylvio Alves <[email protected]>

Author: sylvioalves

soc/riscv/esp32c3/loader.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp32c3/rom/cache.h>
+#include "soc/cache_memory.h"
+#include "soc/extmem_reg.h"
+#include <bootloader_flash_priv.h>
+
+#include <zephyr.h>
+#include <soc.h>
+#include <storage/flash_map.h>
+#include <esp_log.h>
+#include <stdlib.h>
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
+
+extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
+extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
+
+void __start(void);
+
+static HDR_ATTR void (*_entry_point)(void) = &__start;
+
+static int map_rom_segments(void)
+{
+	int rc = 0;
+
+	size_t _partition_offset = FLASH_AREA_OFFSET(image_0);
+	uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
+	uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
+	uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
+
+	uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
+	uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
+	uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
+
+	uint32_t autoload = esp_rom_Cache_Suspend_ICache();
+
+	esp_rom_Cache_Invalidate_ICache_All();
+
+	/* Clear the MMU entries that are already set up,
+	 * so the new app only has the mappings it creates.
+	 */
+	for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
+		FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
+	}
+
+	uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
+
+	rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000,
+				_app_drom_start & 0xffff0000, 64, drom_page_count, 0);
+
+	uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
+
+	rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000,
+				_app_irom_start & 0xffff0000, 64, irom_page_count, 0);
+
+	REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
+	REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
+
+	esp_rom_Cache_Resume_ICache(autoload);
+
+	return rc;
+}
+#endif
+
+void __start(void)
+{
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+	int err = map_rom_segments();
+
+	if (err != 0) {
+		ets_printf("Failed to setup XIP, aborting\n");
+		abort();
+	}
+#endif
+	__esp_platform_start();
+}

soc/riscv/esp32c3/soc.c

@@ -17,18 +17,17 @@
 #include <drivers/interrupt_controller/intc_esp32c3.h>
 
 #include <kernel_structs.h>
+#include <kernel_internal.h>
 #include <string.h>
 #include <toolchain/gcc.h>
 #include <soc.h>
 
-extern void _PrepC(void);
-
 /*
  * This is written in C rather than assembly since, during the port bring up,
  * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
  * is already set up.
  */
-void __attribute__((section(".iram1"))) __start(void)
+void __attribute__((section(".iram1"))) __esp_platform_start(void)
 {
 	volatile uint32_t *wdt_rtc_protect = (uint32_t *)RTC_CNTL_WDTWPROTECT_REG;
 	volatile uint32_t *wdt_rtc_reg = (uint32_t *)RTC_CNTL_WDTCONFIG0_REG;
@@ -47,35 +46,18 @@ void __attribute__((section(".iram1"))) __start(void)
 	__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
 						"csrw mtvec, t0\n");
 
+	z_bss_zero();
+
 	/* Disable normal interrupts. */
 	csr_read_clear(mstatus, MSTATUS_MIE);
 
-#if !CONFIG_BOOTLOADER_ESP_IDF
-	/* The watchdog timer is enabled in the 1st stage (ROM) bootloader.
-	 * We're done booting, so disable it.
-	 * If 2nd stage bootloader from IDF is enabled, then that will take
-	 * care of this.
-	 */
-	volatile uint32_t *wdt_timg_protect = (uint32_t *)TIMG_WDTWPROTECT_REG(0);
-	volatile uint32_t *wdt_timg_reg = (uint32_t *)TIMG_WDTCONFIG0_REG(0);
-
-	*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
-	*wdt_rtc_reg &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
-	*wdt_rtc_protect = 0;
-	*wdt_timg_protect = TIMG_WDT_WKEY_VALUE;
-	*wdt_timg_reg &= ~TIMG_WDT_FLASHBOOT_MOD_EN;
-	*wdt_timg_protect = 0;
-#endif
-
-#if CONFIG_BOOTLOADER_ESP_IDF
 	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
 	 * related issues in application. Hence disable that as we are about to start
 	 * Zephyr environment.
 	 */
 	*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
 	*wdt_rtc_reg &= ~RTC_CNTL_WDT_EN;
 	*wdt_rtc_protect = 0;
-#endif
 
 	/* Configure the Cache MMU size for instruction and rodata in flash. */
 	extern uint32_t esp_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
@@ -105,7 +87,7 @@ void __attribute__((section(".iram1"))) __start(void)
 	esp_intr_initialize();
 
 	/* Start Zephyr */
-	_PrepC();
+	z_cstart();
 
 	CODE_UNREACHABLE;
 }

soc/riscv/esp32c3/soc.h

@@ -35,6 +35,8 @@
 
 #ifndef _ASMLANGUAGE
 
+void __esp_platform_start(void);
+
 extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
 extern void esp_rom_uart_attach(void);
 extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
@@ -48,6 +50,13 @@ extern void esprv_intc_int_set_threshold(int priority_threshold);
 uint32_t soc_intr_get_next_source(void);
 extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
 extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
+extern uint32_t esp_rom_Cache_Suspend_ICache(void);
+extern void esp_rom_Cache_Invalidate_ICache_All(void);
+extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
+				uint32_t psize, uint32_t num, uint32_t fixed);
+extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
+				uint32_t psize, uint32_t num, uint32_t fixed);
+extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
 extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data;
 extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
 				    bool inverted);