arch: riscv: use RISCV_ISA_EXT_F to set CPU_HAS_FPU

maass-hamburg · cfriedt · commit 24669df20789 · 2025-10-24T13:21:47.000-04:00
use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.

Signed-off-by: Fin Maaß &lt;f.maass@vogl-electronic.com&gt;
diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
@@ -45,6 +45,7 @@ config RISCV_ISA_EXT_A
 
 config RISCV_ISA_EXT_F
 	bool
+	select CPU_HAS_FPU
 	help
 	  (F) - Standard Extension for Single-Precision Floating-Point
 
@@ -56,6 +57,7 @@ config RISCV_ISA_EXT_F
 config RISCV_ISA_EXT_D
 	bool
 	depends on RISCV_ISA_EXT_F
+	select CPU_HAS_FPU_DOUBLE_PRECISION
 	help
 	  (D) - Standard Extension for Double-Precision Floating-Point
 
diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig
@@ -61,11 +61,12 @@ config NO_FPU
 
 config SINGLE_PRECISION_FPU
 	bool "Single precision FPU"
-	select CPU_HAS_FPU
+	select RISCV_ISA_EXT_F
 
 config DOUBLE_PRECISION_FPU
 	bool "Double precision FPU"
-	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
 
 endchoice
 
diff --git a/soc/bflb/bl60x/Kconfig b/soc/bflb/bl60x/Kconfig
@@ -8,7 +8,6 @@ config SOC_SERIES_BL60X
 	select CACHE_MANAGEMENT
 	select CLOCK_CONTROL
 	select CODE_DATA_RELOCATION
-	select CPU_HAS_FPU
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select FLOAT_HARD
diff --git a/soc/bflb/bl61x/Kconfig b/soc/bflb/bl61x/Kconfig
@@ -5,7 +5,6 @@
 config SOC_SERIES_BL61X
 	select CLOCK_CONTROL
 	select CODE_DATA_RELOCATION
-	select CPU_HAS_FPU
 	select DCACHE
 	select FLOAT_HARD
 	select FPU
diff --git a/soc/bflb/bl70x/Kconfig b/soc/bflb/bl70x/Kconfig
@@ -7,7 +7,6 @@ config SOC_SERIES_BL70X
 	select CACHE_MANAGEMENT
 	select CLOCK_CONTROL
 	select CODE_DATA_RELOCATION
-	select CPU_HAS_FPU
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select FLOAT_HARD
diff --git a/soc/egis/et171/Kconfig b/soc/egis/et171/Kconfig
@@ -11,9 +11,9 @@ config SOC_EGIS_ET171
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_F
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
-	select CPU_HAS_FPU
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	select CPU_HAS_ANDES_EXECIT
diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_IT8XXX2
-	select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_F if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
 	select HAS_PM
 	select ARCH_HAS_CUSTOM_CPU_IDLE
 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig b/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig
@@ -2,8 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_QEMU_VIRT_RISCV32
-	select CPU_HAS_FPU
 	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_F
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_PLIC
diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig b/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_QEMU_VIRT_RISCV64
-	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_PLIC
diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig b/soc/sifive/sifive_freedom/fu500/Kconfig
@@ -26,4 +26,3 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
 config SOC_SIFIVE_FREEDOM_FU540_U54
 	bool
 	select RISCV_ISA_EXT_G
-	select CPU_HAS_FPU_DOUBLE_PRECISION
diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig b/soc/sifive/sifive_freedom/fu700/Kconfig
@@ -25,4 +25,3 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700
 config SOC_SIFIVE_FREEDOM_FU740_U74
 	bool
 	select RISCV_ISA_EXT_G
-	select CPU_HAS_FPU_DOUBLE_PRECISION
diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig
@@ -8,13 +8,13 @@ config SOC_SERIES_TLSR951X
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_F
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select HAS_TELINK_DRIVERS
-	select CPU_HAS_FPU
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	select CPU_HAS_ANDES_HWDSP
