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Martinhoff-makerMartinhoff-maker
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samples/tests: adc: silabs: add multiple device overlays.
This commit introduces/updates overlays for multiple silabs boards for ADC samples and ADC tests. Signed-off-by: Martin Hoff <[email protected]>
1 parent d21081f commit 2470784

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+992
-18
lines changed

‎samples/drivers/adc/adc_dt/boards/bg29_rb4420a.overlay‎

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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "dt-bindings/adc/silabs-adc.h"
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/ {
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zephyr,user {
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io-channels = <&adc0 0>, <&adc0 1>;
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};
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};
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&adc0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_IOVDD>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_VBAT>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/sltb010a.overlay‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*/
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#include <dt-bindings/adc/silabs-adc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 3>, <&adc0 4>;
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};
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};
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&pinctrl {
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adc0_default: adc0_default {
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group0 {
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/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
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silabs,analog-bus = <ABUS_BODD0_IADC0>;
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};
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};
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};
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&adc0 {
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pinctrl-0 = <&adc0_default>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_VDD_1";
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zephyr,vref-mv = <3000>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_PB3>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/slwrb4180a.overlay‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*/
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#include <dt-bindings/adc/silabs-adc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 3>, <&adc0 4>;
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};
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};
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&pinctrl {
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adc0_default: adc0_default {
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group0 {
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/* Allocate odd bus 0 on GPIO port C/D to IADC for access to pin PD3 */
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silabs,analog-bus = <ABUS_CDODD0_IADC0>;
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};
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};
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};
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&adc0 {
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pinctrl-0 = <&adc0_default>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_VDD_1";
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zephyr,vref-mv = <3300>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_PD3>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/xg23_rb4210a.overlay‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*/
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#include <dt-bindings/adc/silabs-adc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 3>, <&adc0 4>;
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};
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};
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&pinctrl {
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adc0_default: adc0_default {
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group0 {
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/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
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silabs,analog-bus = <ABUS_BODD0_IADC0>;
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};
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};
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};
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&adc0 {
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pinctrl-0 = <&adc0_default>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_VDD_1";
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zephyr,vref-mv = <3300>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_PB3>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/xg24_rb4187c.overlay‎

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@@ -4,7 +4,6 @@
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*/
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7-
#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
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#include <dt-bindings/adc/silabs-adc.h>
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/ {

‎samples/drivers/adc/adc_dt/boards/xg27_dk2602a.overlay‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*/
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#include <dt-bindings/adc/silabs-adc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 3>, <&adc0 4>;
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};
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};
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&pinctrl {
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adc0_default: adc0_default {
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group0 {
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/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
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silabs,analog-bus = <ABUS_BODD0_IADC0>;
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};
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};
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};
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&adc0 {
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pinctrl-0 = <&adc0_default>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_VDD_1";
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zephyr,vref-mv = <3300>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_PB3>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay‎

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@@ -34,7 +34,8 @@
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,oversampling = <5>;
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zephyr,resolution = <16>;
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zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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zephyr,reference = "ADC_REF_VDD_1";
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zephyr,vref-mv = <3300>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,oversampling = <5>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_PD3>;
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};

‎samples/drivers/adc/adc_dt/sample.yaml‎

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- mcx_n9xx_evk/mcxn947/cpu0
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- frdm_mcxc242
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- ucans32k1sic
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- sltb010a
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- slwrb4180a
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- xg23_rb4210a
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- xg24_rb4187c
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- xg27_dk2602a
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- xg29_rb4412a
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- bg29_rb4420a
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- raytac_an54l15q_db/nrf54l15/cpuapp
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- frdm_mcxa346
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- frdm_mcxa266

‎samples/drivers/adc/adc_sequence/boards/bg29_rb4420a.overlay‎

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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "dt-bindings/adc/silabs-adc.h"
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/ {
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zephyr,user {
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io-channels = <&adc0 0>, <&adc0 1>;
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};
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aliases {
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adc0 = &adc0;
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};
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};
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&adc0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
27+
zephyr,reference = "ADC_REF_INTERNAL";
28+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
29+
zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_IOVDD>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,input-positive = <IADC_INPUT_VBAT>;
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};
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};

‎samples/drivers/adc/adc_sequence/boards/sltb010a.overlay‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Silicon Laboratories Inc.
5+
*/
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7+
#include <dt-bindings/adc/silabs-adc.h>
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 3>, <&adc0 4>;
12+
};
13+
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aliases {
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adc0 = &adc0;
16+
};
17+
};
18+
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&pinctrl {
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adc0_default: adc0_default {
21+
group0 {
22+
/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
23+
silabs,analog-bus = <ABUS_BODD0_IADC0>;
24+
};
25+
};
26+
};
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&adc0 {
29+
pinctrl-0 = <&adc0_default>;
30+
pinctrl-names = "default";
31+
#address-cells = <1>;
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#size-cells = <0>;
33+
status = "okay";
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channel@3 {
36+
reg = <3>;
37+
zephyr,gain = "ADC_GAIN_1";
38+
zephyr,reference = "ADC_REF_INTERNAL";
39+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
41+
zephyr,input-positive = <IADC_INPUT_AVDD>;
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};
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channel@4 {
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reg = <4>;
46+
zephyr,gain = "ADC_GAIN_1";
47+
zephyr,reference = "ADC_REF_VDD_1";
48+
zephyr,vref-mv = <3000>;
49+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
50+
zephyr,resolution = <12>;
51+
zephyr,input-positive = <IADC_INPUT_PB3>;
52+
};
53+
};

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