sam0: move the UART and SPI configuration into pinmux.

nzmichaelh · galak · commit 247782a7b36b · 2018-02-08T12:09:46.000-06:00
Also pull out the SERCOM pads configuration to defines.  Note that the
SAM0 has a two level configuration - a signal (like TX) is mapped to a
pad, and then a pad is mapped to a function on a pin.

Signed-off-by: Michael Hope &lt;mlhx@google.com&gt;
diff --git a/arch/arm/soc/atmel_sam0/samd/soc.c b/arch/arm/soc/atmel_sam0/samd/soc.c
@@ -16,18 +16,6 @@
 #include <kernel.h>
 #include <soc.h>
 
-void soc_gpio_configure(const struct soc_gpio_pin *pin)
-{
-	PortGroup *group = &PORT->Group[pin->group];
-
-	if ((pin->pin & 1) == 0) {
-		group->PMUX[pin->pin / 2].bit.PMUXE = pin->mux;
-	} else {
-		group->PMUX[pin->pin / 2].bit.PMUXO = pin->mux;
-	}
-	group->PINCFG[pin->pin].bit.PMUXEN = 1;
-}
-
 static void flash_waitstates_init(void)
 {
 	/* One wait state at 48 MHz. */
diff --git a/arch/arm/soc/atmel_sam0/samd/soc.h b/arch/arm/soc/atmel_sam0/samd/soc.h
@@ -45,16 +45,6 @@
 #error Library does not support the specified device.
 #endif
 
-#include "soc_pinmap.h"
-
-struct soc_gpio_pin {
-	u8_t group;
-	u8_t pin;
-	u8_t mux;
-};
-
-void soc_gpio_configure(const struct soc_gpio_pin *pin);
-
 #endif /* _ASMLANGUAGE */
 
 /** Processor Clock (HCLK) Frequency */
diff --git a/arch/arm/soc/atmel_sam0/samd/soc_pinmap.h b/arch/arm/soc/atmel_sam0/samd/soc_pinmap.h
diff --git a/boards/arm/arduino_zero/CMakeLists.txt b/boards/arm/arduino_zero/CMakeLists.txt
@@ -0,0 +1,4 @@
+if(CONFIG_PINMUX_SAM0)
+  zephyr_library()
+  zephyr_library_sources(pinmux.c)
+endif()
diff --git a/boards/arm/arduino_zero/board.h b/boards/arm/arduino_zero/board.h
@@ -21,4 +21,12 @@
 #define LED2_GPIO_PORT	CONFIG_GPIO_SAM0_PORTB_LABEL
 #define LED2_GPIO_PIN	3
 
+#define CONFIG_UART_SAM0_SERCOM0_PADS \
+	(SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1))
+#define CONFIG_UART_SAM0_SERCOM5_PADS \
+	(SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1))
+
+#define CONFIG_SPI_SAM0_SERCOM4_PADS \
+	(SERCOM_SPI_CTRLA_DIPO(0) | SERCOM_SPI_CTRLA_DOPO(1))
+
 #endif /* __INC_BOARD_H */
diff --git a/boards/arm/arduino_zero/pinmux.c b/boards/arm/arduino_zero/pinmux.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 Google LLC.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <pinmux.h>
+
+static int board_pinmux_init(struct device *dev)
+{
+	struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL);
+	struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL);
+
+	ARG_UNUSED(dev);
+
+#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS
+	/* SERCOM0 on RX=PA11, TX=PA10 */
+	pinmux_pin_set(muxa, 11, PINMUX_FUNC_C);
+	pinmux_pin_set(muxa, 10, PINMUX_FUNC_C);
+#endif
+
+#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS
+	/* SERCOM5 on RX=PB23, TX=PB22 */
+	pinmux_pin_set(muxb, 23, PINMUX_FUNC_D);
+	pinmux_pin_set(muxb, 22, PINMUX_FUNC_D);
+#endif
+
+#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+
+#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS
+	/* SPI SERCOM4 on MISO=PB12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */
+	pinmux_pin_set(muxb, 12, PINMUX_FUNC_C);
+	pinmux_pin_set(muxb, 10, PINMUX_FUNC_D);
+	pinmux_pin_set(muxb, 11, PINMUX_FUNC_D);
+#endif
+
+#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS
+#error Pin mapping is not configured
+#endif
+
+	return 0;
+}
+
+SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);
diff --git a/drivers/serial/uart_sam0.c b/drivers/serial/uart_sam0.c
@@ -10,16 +10,15 @@
 #include <misc/__assert.h>
 #include <soc.h>
 #include <uart.h>
+#include <board.h>
 
 /* Device constant configuration parameters */
 struct uart_sam0_dev_cfg {
 	SercomUsart *regs;
 	u32_t baudrate;
-	u32_t ctrla;
+	u32_t pads;
 	u32_t pm_apbcmask;
 	u16_t gclk_clkctrl_id;
-	struct soc_gpio_pin pin_rx;
-	struct soc_gpio_pin pin_tx;
 #if CONFIG_UART_INTERRUPT_DRIVEN
 	void (*irq_config_func)(struct device *dev);
 #endif
@@ -76,17 +75,13 @@ static int uart_sam0_init(struct device *dev)
 	/* Enable SERCOM clock in PM */
 	PM->APBCMASK.reg |= cfg->pm_apbcmask;
 
-	/* Connect pins to the peripheral */
-	soc_gpio_configure(&cfg->pin_rx);
-	soc_gpio_configure(&cfg->pin_tx);
-
 	/* Disable all USART interrupts */
 	usart->INTENCLR.reg = SERCOM_USART_INTENCLR_MASK;
 	wait_synchronization(usart);
 
 	/* 8 bits of data, no parity, 1 stop bit in normal mode */
 	usart->CTRLA.reg =
-	    cfg->ctrla |
+	    cfg->pads |
 	    /* Internal clock */
 	    SERCOM_USART_CTRLA_MODE_USART_INT_CLK
 	    /* 16x oversampling with arithmetic baud rate generation */
@@ -285,9 +280,7 @@ static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		       \
 	.baudrate = CONFIG_UART_SAM0_SERCOM##n##_CURRENT_SPEED,		       \
 	.pm_apbcmask = PM_APBCMASK_SERCOM##n,				       \
 	.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE,		       \
-	.ctrla = SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1),      \
-	.pin_rx = PIN_UART_SAM0_SERCOM##n##_RX,				       \
-	.pin_tx = PIN_UART_SAM0_SERCOM##n##_TX,				       \
+	.pads = CONFIG_UART_SAM0_SERCOM##n##_PADS,			       \
 	UART_SAM0_IRQ_HANDLER_FUNC(n)					       \
 }
 
diff --git a/drivers/spi/spi_sam0.c b/drivers/spi/spi_sam0.c
@@ -8,12 +8,11 @@
 #include <logging/sys_log.h>
 
 #include "spi_context.h"
-#include <device.h>
 #include <errno.h>
-#include <init.h>
-#include <misc/__assert.h>
-#include <soc.h>
+#include <device.h>
 #include <spi.h>
+#include <soc.h>
+#include <board.h>
 
 #if defined(CONFIG_SPI_LEGACY_API)
 #error "This driver does not support the SPI legacy API."
@@ -22,12 +21,9 @@
 /* Device constant configuration parameters */
 struct spi_sam0_config {
 	SercomSpi *regs;
-	u32_t ctrla;
+	u32_t pads;
 	u32_t pm_apbcmask;
 	u16_t gclk_clkctrl_id;
-	struct soc_gpio_pin pin_miso;
-	struct soc_gpio_pin pin_mosi;
-	struct soc_gpio_pin pin_sck;
 };
 
 /* Device run time data */
@@ -77,13 +73,11 @@ static int spi_sam0_configure(struct spi_config *config)
 		ctrla.bit.CPHA = 1;
 	}
 
-	/* MOSI on PAD2, SCK on PAD3 */
-	ctrla.bit.DOPO = 1;
+	ctrla.reg |= cfg->pads;
 
 	if ((config->operation & SPI_MODE_LOOP) != 0) {
-		/* Put MISO on the same pin as MOSI */
-		ctrla.bit.DIPO = 2;
-	} else {
+		/* Put MISO and MOSI on the same pad */
+		ctrla.bit.DOPO = 0;
 		ctrla.bit.DIPO = 0;
 	}
 
@@ -419,11 +413,6 @@ static int spi_sam0_init(struct device *dev)
 	/* Enable SERCOM clock in PM */
 	PM->APBCMASK.reg |= cfg->pm_apbcmask;
 
-	/* Connect pins to the peripheral */
-	soc_gpio_configure(&cfg->pin_mosi);
-	soc_gpio_configure(&cfg->pin_miso);
-	soc_gpio_configure(&cfg->pin_sck);
-
 	/* Disable all SPI interrupts */
 	regs->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
 	wait_synchronization(regs);
@@ -450,11 +439,7 @@ static const struct spi_driver_api spi_sam0_driver_api = {
 		.regs = &SERCOM##n->SPI,                                     \
 		.pm_apbcmask = PM_APBCMASK_SERCOM##n,                        \
 		.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE,         \
-		.ctrla = SERCOM_USART_CTRLA_RXPO(3) |                        \
-			 SERCOM_USART_CTRLA_TXPO(1),                         \
-		.pin_miso = PIN_SPI_SAM0_SERCOM##n##_MISO,                   \
-		.pin_mosi = PIN_SPI_SAM0_SERCOM##n##_MOSI,                   \
-		.pin_sck = PIN_SPI_SAM0_SERCOM##n##_SCK,                     \
+		.pads = CONFIG_SPI_SAM0_SERCOM##n##_PADS                     \
 	}
 
 #define SPI_SAM0_DEVICE_INIT(n)                                              \
