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#define NUMBER_OF_CHANNELS 1
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struct pwm_litex_cfg {
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- uint32_t reg_en_size ;
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- uint32_t reg_width_size ;
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- uint32_t reg_period_size ;
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- volatile uint32_t * reg_en ;
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- volatile uint32_t * reg_width ;
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- volatile uint32_t * reg_period ;
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+ uint32_t reg_en ;
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+ uint32_t reg_width ;
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+ uint32_t reg_period ;
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};
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- static void litex_set_reg (volatile uint32_t * reg , uint32_t reg_size , uint32_t val )
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- {
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- uint32_t shifted_data ;
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- volatile uint32_t * reg_addr ;
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-
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- for (int i = 0 ; i < reg_size ; ++ i ) {
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- shifted_data = val >> ((reg_size - i - 1 ) * 8 );
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- reg_addr = ((volatile uint32_t * ) reg ) + i ;
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- * (reg_addr ) = shifted_data ;
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- }
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- }
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-
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int pwm_litex_init (const struct device * dev )
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{
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const struct pwm_litex_cfg * cfg = dev -> config ;
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- litex_set_reg ( cfg -> reg_en , cfg -> reg_en_size , REG_EN_ENABLE );
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+ litex_write8 ( REG_EN_ENABLE , cfg -> reg_en );
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return 0 ;
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}
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@@ -55,10 +40,10 @@ int pwm_litex_set_cycles(const struct device *dev, uint32_t channel,
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return - EINVAL ;
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}
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- litex_set_reg ( cfg -> reg_en , cfg -> reg_en_size , REG_EN_DISABLE );
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- litex_set_reg ( cfg -> reg_width , cfg -> reg_width_size , pulse_cycles );
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- litex_set_reg ( cfg -> reg_period , cfg -> reg_period_size , period_cycles );
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- litex_set_reg ( cfg -> reg_en , cfg -> reg_en_size , REG_EN_ENABLE );
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+ litex_write8 ( REG_EN_DISABLE , cfg -> reg_en );
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+ litex_write32 ( pulse_cycles , cfg -> reg_width );
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+ litex_write32 ( period_cycles , cfg -> reg_period );
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+ litex_write8 ( REG_EN_ENABLE , cfg -> reg_en );
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return 0 ;
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}
@@ -81,25 +66,11 @@ static const struct pwm_driver_api pwm_litex_driver_api = {
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/* Device Instantiation */
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- /* LiteX registers use only first byte from 4-bytes register, that's why they
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- * occupy larger space in memory. We need to know the size that is
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- * actually used, that is why the register size from dts is divided by 4.
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- */
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-
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#define PWM_LITEX_INIT (n ) \
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static const struct pwm_litex_cfg pwm_litex_cfg_##n = { \
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- .reg_en = \
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- (volatile uint32_t *) \
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- DT_INST_REG_ADDR_BY_NAME(n, enable), \
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- .reg_en_size = DT_INST_REG_SIZE_BY_NAME(n, enable) / 4, \
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- .reg_width = \
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- (volatile uint32_t *) \
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- DT_INST_REG_ADDR_BY_NAME(n, width), \
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- .reg_width_size = DT_INST_REG_SIZE_BY_NAME(n, width) / 4, \
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- .reg_period = \
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- (volatile uint32_t *) \
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- DT_INST_REG_ADDR_BY_NAME(n, period), \
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- .reg_period_size = DT_INST_REG_SIZE_BY_NAME(n, period) / 4, \
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+ .reg_en = DT_INST_REG_ADDR_BY_NAME(n, enable), \
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+ .reg_width = DT_INST_REG_ADDR_BY_NAME(n, width), \
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+ .reg_period = DT_INST_REG_ADDR_BY_NAME(n, period), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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