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dts: Add MSPI configuration for STM32
This commit adds the main DTS configurations required to enable MSPI/OSPI/QSPI support on STM32. Signed-off-by: Sara Touqan <[email protected]> Signed-off-by: Sarah Younis <[email protected]> Signed-off-by: Mohammad Odeh <[email protected]>
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‎dts/bindings/mspi/st,stm32-mspi-controller.yaml‎

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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 MSPI controller representation. Enabling a stm32 mspi node in a board
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description would typically requires this: (pinning depends on the stm32 mcu)
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&mspi {
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pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
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&octospi_io0_pe12 &octospi_io1_pe13
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&octospi_io2_pe14 &octospi_io3_pe15
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&octospi_io4_pe16 &octospi_io5_pe17
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&octospi_io6_pe18 &octospi_io7_pe19>;
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dmas = <&dma1 5 41 0x10000>;
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dma-names = "tx_rx";
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status = "okay";
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};
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compatible: "st,stm32-mspi-controller"
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include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
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bus: mspi
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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clock-names:
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required: true
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dmas:
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description: |
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Optional DMA channel specifier, required for DMA transactions.
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For example dmas for TX/RX on MSPI
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dmas = <&dma1 5 41 0x10000>;
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With, in each cell of the dmas specifier:
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- &dma1: dma controller phandle
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- 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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- 41: slot number (request which could be given by the DMAMUX)
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- 0x10000: channel configuration (only for srce/dest data size, priority)
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Notes:
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- On series supporting DMAMUX, the DMA phandle should be provided
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but DMAMUX node should also be enabled in the DTS.
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- For channel configuration, only the config bits priority and
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periph/mem datasize are used. The periph/mem datasize must be equal,
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0 is a correct value.
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- There is no Fifo used by this DMA peripheral.
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For example dmas for TX/RX on MSPI
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dmas = <&dma1 5 41 0x10000>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx_rx".
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For example
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dma-names = "tx_rx";
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ssht-enable:
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type: boolean
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description: |
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Enables Sample Shifting half-cycle.
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It is recommended to be enabled in STR mode and disabled in DTR mode.

‎dts/bindings/mspi/st,stm32-ospi-controller.yaml‎

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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 MSPI controller representation. Enabling a stm32 mspi node in a board
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description would typically requires this: (pinning depends on the stm32 mcu)
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&ospi {
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pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
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&octospi_io0_pe12 &octospi_io1_pe13
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&octospi_io2_pe14 &octospi_io3_pe15
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&octospi_io4_pe16 &octospi_io5_pe17
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&octospi_io6_pe18 &octospi_io7_pe19>;
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dmas = <&dma1 5 41 0x10000>;
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dma-names = "tx_rx";
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status = "okay";
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};
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compatible: "st,stm32-ospi-controller"
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include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
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bus: mspi
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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clock-names:
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required: true
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dmas:
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description: |
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Optional DMA channel specifier, required for DMA transactions.
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For example dmas for TX/RX on MSPI
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dmas = <&dma1 5 41 0x10000>;
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With, in each cell of the dmas specifier:
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- &dma1: dma controller phandle
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- 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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- 41: slot number (request which could be given by the DMAMUX)
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- 0x10000: channel configuration (only for srce/dest data size, priority)
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Notes:
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- On series supporting DMAMUX, the DMA phandle should be provided
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but DMAMUX node should also be enabled in the DTS.
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- For channel configuration, only the config bits priority and
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periph/mem datasize are used. The periph/mem datasize must be equal,
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0 is a correct value.
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- There is no Fifo used by this DMA peripheral.
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For example dmas for TX/RX on MSPI
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dmas = <&dma1 5 41 0x10000>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx_rx".
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For example
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dma-names = "tx_rx";
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dlyb-bypass:
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type: boolean
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description: |
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Enables Delay Block (DLYB) Bypass.
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ssht-enable:
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type: boolean
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description: |
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Enables Sample Shifting half-cycle.
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It is recommended to be enabled in STR mode and disabled in DTR mode.
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io-low-port:
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type: string
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enum:
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- "IOPORT_NONE"
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- "IOPORT_1_LOW"
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- "IOPORT_1_HIGH"
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- "IOPORT_2_LOW"
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- "IOPORT_2_HIGH"
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the IO[3:0] pins.
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If absent, then `IOPORT_<n>_LOW` is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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io-high-port:
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type: string
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enum:
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- "IOPORT_NONE"
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- "IOPORT_1_LOW"
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- "IOPORT_1_HIGH"
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- "IOPORT_2_LOW"
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- "IOPORT_2_HIGH"
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the IO[7:4] pins.
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If absent, then `IOPORT_<n>_HIGH` is used where `n` is the OSPI
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instance number.
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Can be set to `IOPORT_NONE` for Single SPI, Dual SPI and Quad SPI.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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clk-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the clk pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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dqs-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the dqs pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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ncs-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the ncs pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.

‎dts/bindings/mspi/st,stm32-qspi-controller.yaml‎

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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 QSPI controller representation for MSPI interface. Enabling a stm32 qspi node
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in a board description would typically require this: (pinning depends on the stm32 mcu)
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&qspi {
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pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
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&quadspi_io0_pe12 &quadspi_io1_pe13
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&quadspi_io2_pe14 &quadspi_io3_pe15>;
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dmas = <&dma1 5 41 0x10000>;
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dma-names = "tx_rx";
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status = "okay";
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};
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compatible: "st,stm32-qspi-controller"
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include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
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bus: mspi
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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clock-names:
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required: true
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dmas:
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description: |
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Optional DMA channel specifier, required for DMA transactions.
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For example dmas for TX/RX on QSPI
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dmas = <&dma1 5 41 0x10000>;
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With, in each cell of the dmas specifier:
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- &dma1: dma controller phandle
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- 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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- 41: slot number (request which could be given by the DMAMUX)
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- 0x10000: channel configuration (only for src/dest data size, priority)
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Notes:
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- On series supporting DMAMUX, the DMA phandle should be provided
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but DMAMUX node should also be enabled in the DTS.
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- For channel configuration, only the config bits priority and
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periph/mem datasize are used. The periph/mem datasize must be equal,
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0 is a correct value.
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- There is no Fifo used by this DMA peripheral.
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For example dmas for TX/RX on QSPI
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dmas = <&dma1 5 41 0x10000>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx_rx".
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For example
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dma-names = "tx_rx";
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ssht-enable:
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type: boolean
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description: |
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Enables Sample Shifting half-cycle.
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It is recommended to be enabled in STR mode and disabled in DTR mode.
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Note: DTR support is limited on QSPI compared to OCTOSPI/XSPI.
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flash-id:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which flash device is selected (for dual flash configurations).
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If absent, then flash 1 is used.
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dual-flash:
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type: boolean
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description: |
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Enables dual flash mode where two identical flash devices are connected
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to provide doubled capacity and/or performance.
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Note: This is only supported on certain STM32 QSPI implementations.
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fifo-threshold:
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type: int
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description: |
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FIFO threshold for QSPI operations. This determines when the FIFO
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threshold flag is set during indirect read/write operations.
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Valid range is typically 1-32 bytes depending on QSPI implementation.
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Default is 4 bytes if not specified.
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chip-select-high-time:
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type: int
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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description: |
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Specifies the minimum number of clock cycles that the chip select (nCS)
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must remain high between commands.
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Default is 1 cycle if not specified.
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clock-mode:
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type: int
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enum:
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- 0
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- 3
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description: |
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Specifies the clock mode (CPOL/CPHA combination):
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- 0: Clock stays low when nCS is released (CPOL=0, CPHA=0)
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- 3: Clock goes high when nCS is released (CPOL=1, CPHA=1)
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Default is mode 0 if not specified.

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