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drivers: mipi_dbi: add support for parallel 8080/6800 modes using GPIO
Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI type A and B displays to be used on general platforms. Since each data pin GPIO can be selected individually, the bus pins are set in a loop, which has a significant negative impact on performance. When using 8-bit mode and all the data GPIO pins are on the same port, a look-up table is generated to set the whole port at once as a performance optimization. This creates a ROM overhead of about 1 kiB. Tested 8-bit 8080 mode with ILI9486 display on nRF52840-DK board. Signed-off-by: Stefan Gloor <[email protected]>
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‎drivers/mipi_dbi/CMakeLists.txt‎

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@@ -3,6 +3,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_MIPI_DBI_SPI mipi_dbi_spi.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DBI_BITBANG mipi_dbi_bitbang.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DBI_SMARTBOND mipi_dbi_smartbond.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_LCDIC mipi_dbi_nxp_lcdic.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF mipi_dbi_nxp_flexio_lcdif.c)

‎drivers/mipi_dbi/Kconfig‎

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@@ -22,6 +22,7 @@ config MIPI_DBI_INIT_PRIORITY
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MIPI-DBI Host Controllers initialization priority.
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source "drivers/mipi_dbi/Kconfig.spi"
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source "drivers/mipi_dbi/Kconfig.bitbang"
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source "drivers/mipi_dbi/Kconfig.smartbond"
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source "drivers/mipi_dbi/Kconfig.nxp_lcdic"
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source "drivers/mipi_dbi/Kconfig.nxp_flexio_lcdif"

‎drivers/mipi_dbi/Kconfig.bitbang‎

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# Copyright 2024 Stefan Gloor
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# SPDX-License-Identifier: Apache-2.0
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config MIPI_DBI_BITBANG
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bool "MIPI DBI bit banging driver"
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default y
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depends on DT_HAS_ZEPHYR_MIPI_DBI_BITBANG_ENABLED
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select GPIO
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help
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Enable support for MIPI DBI bit banging driver. This driver implements
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a MIPI-DBI mode A and B compatible controller using GPIO.

‎drivers/mipi_dbi/mipi_dbi_bitbang.c‎

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/*
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* MIPI DBI Type A and B driver using GPIO
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*
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* Copyright 2024 Stefan Gloor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT zephyr_mipi_dbi_bitbang
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#include <zephyr/drivers/mipi_dbi.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(mipi_dbi_bitbang, CONFIG_MIPI_DBI_LOG_LEVEL);
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/* The MIPI DBI spec allows 8, 9, and 16 bits */
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#define MIPI_DBI_MAX_DATA_BUS_WIDTH 16
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/* Compile in a data bus LUT for improved performance if at least one instance uses an 8-bit bus */
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#define _8_BIT_MODE_PRESENT(n) (DT_INST_PROP_LEN(n, data_gpios) == 8) |
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#define MIPI_DBI_8_BIT_MODE DT_INST_FOREACH_STATUS_OKAY(_8_BIT_MODE_PRESENT) 0
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struct mipi_dbi_bitbang_config {
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/* Parallel 8080/6800 data GPIOs */
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const struct gpio_dt_spec data[MIPI_DBI_MAX_DATA_BUS_WIDTH];
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const uint8_t data_bus_width;
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/* Read (type B) GPIO */
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const struct gpio_dt_spec rd;
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/* Write (type B) or Read/!Write (type A) GPIO */
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const struct gpio_dt_spec wr;
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/* Enable/strobe GPIO (type A) */
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const struct gpio_dt_spec e;
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/* Chip-select GPIO */
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const struct gpio_dt_spec cs;
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/* Command/Data GPIO */
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const struct gpio_dt_spec cmd_data;
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/* Reset GPIO */
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const struct gpio_dt_spec reset;
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#if MIPI_DBI_8_BIT_MODE
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/* Data GPIO remap look-up table. Valid if mipi_dbi_bitbang_data.single_port is set */
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const uint32_t data_lut[256];
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/* Mask of all data pins. Valid if mipi_dbi_bitbang_data.single_port is set */
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const uint32_t data_mask;
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#endif
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};
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struct mipi_dbi_bitbang_data {
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struct k_mutex lock;
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#if MIPI_DBI_8_BIT_MODE
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/* Indicates whether all data GPIO pins are on the same port and the data LUT is used. */
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bool single_port;
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/* Data GPIO port device. Valid if mipi_dbi_bitbang_data.single_port is set */
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const struct device *data_port;
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#endif
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};
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static inline void mipi_dbi_bitbang_set_data_gpios(const struct mipi_dbi_bitbang_config *config,
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struct mipi_dbi_bitbang_data *data,
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uint32_t value)
71+
{
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#if MIPI_DBI_8_BIT_MODE
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if (data->single_port) {
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gpio_port_set_masked(data->data_port, config->data_mask, config->data_lut[value]);
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} else {
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#endif
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for (int i = 0; i < config->data_bus_width; i++) {
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gpio_pin_set_dt(&config->data[i], (value & (1 << i)) != 0);
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}
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#if MIPI_DBI_8_BIT_MODE
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}
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#endif
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}
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static int mipi_dbi_bitbang_write_helper(const struct device *dev,
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const struct mipi_dbi_config *dbi_config, bool cmd_present,
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uint8_t cmd, const uint8_t *data_buf, size_t len)
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{
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const struct mipi_dbi_bitbang_config *config = dev->config;
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struct mipi_dbi_bitbang_data *data = dev->data;
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int ret = 0;
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uint8_t value;
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ret = k_mutex_lock(&data->lock, K_FOREVER);
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if (ret < 0) {
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return ret;
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}
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switch (dbi_config->mode) {
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case MIPI_DBI_MODE_8080_BUS_8_BIT:
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case MIPI_DBI_MODE_8080_BUS_9_BIT:
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case MIPI_DBI_MODE_8080_BUS_16_BIT:
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gpio_pin_set_dt(&config->cs, 1);
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if (cmd_present) {
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gpio_pin_set_dt(&config->wr, 0);
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gpio_pin_set_dt(&config->cmd_data, 0);
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mipi_dbi_bitbang_set_data_gpios(config, data, cmd);
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gpio_pin_set_dt(&config->wr, 1);
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}
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if (len > 0) {
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gpio_pin_set_dt(&config->cmd_data, 1);
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while (len > 0) {
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value = *(data_buf++);
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gpio_pin_set_dt(&config->wr, 0);
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mipi_dbi_bitbang_set_data_gpios(config, data, value);
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gpio_pin_set_dt(&config->wr, 1);
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len--;
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}
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}
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gpio_pin_set_dt(&config->cs, 0);
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break;
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/* Clocked E mode */
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case MIPI_DBI_MODE_6800_BUS_8_BIT:
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case MIPI_DBI_MODE_6800_BUS_9_BIT:
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case MIPI_DBI_MODE_6800_BUS_16_BIT:
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gpio_pin_set_dt(&config->cs, 1);
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gpio_pin_set_dt(&config->wr, 0);
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if (cmd_present) {
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gpio_pin_set_dt(&config->e, 1);
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gpio_pin_set_dt(&config->cmd_data, 0);
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mipi_dbi_bitbang_set_data_gpios(config, data, cmd);
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gpio_pin_set_dt(&config->e, 0);
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}
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if (len > 0) {
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gpio_pin_set_dt(&config->cmd_data, 1);
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while (len > 0) {
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value = *(data_buf++);
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gpio_pin_set_dt(&config->e, 1);
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mipi_dbi_bitbang_set_data_gpios(config, data, value);
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gpio_pin_set_dt(&config->e, 0);
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len--;
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}
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}
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gpio_pin_set_dt(&config->cs, 0);
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break;
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default:
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LOG_ERR("MIPI DBI mode %u is not supported.", dbi_config->mode);
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ret = -ENOTSUP;
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}
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k_mutex_unlock(&data->lock);
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return ret;
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}
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static int mipi_dbi_bitbang_command_write(const struct device *dev,
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const struct mipi_dbi_config *dbi_config, uint8_t cmd,
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const uint8_t *data_buf, size_t len)
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{
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return mipi_dbi_bitbang_write_helper(dev, dbi_config, true, cmd, data_buf, len);
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}
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static int mipi_dbi_bitbang_write_display(const struct device *dev,
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const struct mipi_dbi_config *dbi_config,
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const uint8_t *framebuf,
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struct display_buffer_descriptor *desc,
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enum display_pixel_format pixfmt)
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{
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ARG_UNUSED(pixfmt);
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return mipi_dbi_bitbang_write_helper(dev, dbi_config, false, 0x0, framebuf, desc->buf_size);
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}
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static int mipi_dbi_bitbang_reset(const struct device *dev, k_timeout_t delay)
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{
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const struct mipi_dbi_bitbang_config *config = dev->config;
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int ret;
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LOG_DBG("Performing hw reset.");
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ret = gpio_pin_set_dt(&config->reset, 1);
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if (ret < 0) {
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return ret;
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}
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k_sleep(delay);
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return gpio_pin_set_dt(&config->reset, 0);
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}
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static int mipi_dbi_bitbang_init(const struct device *dev)
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{
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const struct mipi_dbi_bitbang_config *config = dev->config;
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const char *failed_pin = NULL;
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int ret = 0;
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#if MIPI_DBI_8_BIT_MODE
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struct mipi_dbi_bitbang_data *data = dev->data;
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#endif
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if (gpio_is_ready_dt(&config->cmd_data)) {
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ret = gpio_pin_configure_dt(&config->cmd_data, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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failed_pin = "cmd_data";
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goto fail;
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}
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gpio_pin_set_dt(&config->cmd_data, 0);
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}
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if (gpio_is_ready_dt(&config->rd)) {
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gpio_pin_configure_dt(&config->rd, GPIO_OUTPUT_ACTIVE);
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/* Don't emit an error because this pin is unused in type A */
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gpio_pin_set_dt(&config->rd, 1);
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}
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if (gpio_is_ready_dt(&config->wr)) {
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ret = gpio_pin_configure_dt(&config->wr, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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failed_pin = "wr";
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goto fail;
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}
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gpio_pin_set_dt(&config->wr, 1);
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}
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if (gpio_is_ready_dt(&config->e)) {
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gpio_pin_configure_dt(&config->e, GPIO_OUTPUT_ACTIVE);
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/* Don't emit an error because this pin is unused in type B */
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gpio_pin_set_dt(&config->e, 0);
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}
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if (gpio_is_ready_dt(&config->cs)) {
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ret = gpio_pin_configure_dt(&config->cs, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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failed_pin = "cs";
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goto fail;
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}
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gpio_pin_set_dt(&config->cs, 0);
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}
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if (gpio_is_ready_dt(&config->reset)) {
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ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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failed_pin = "reset";
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goto fail;
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}
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gpio_pin_set_dt(&config->reset, 0);
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}
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for (int i = 0; i < config->data_bus_width; i++) {
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if (gpio_is_ready_dt(&config->data[i])) {
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ret = gpio_pin_configure_dt(&config->data[i], GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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failed_pin = "data";
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goto fail;
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}
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gpio_pin_set_dt(&config->data[i], 0);
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}
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}
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#if MIPI_DBI_8_BIT_MODE
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/* To optimize performance, we test whether all the data pins are
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* on the same port. If they are, we can set the whole port in one go
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* instead of setting each pin individually.
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* For 8-bit mode only because LUT size grows exponentially.
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*/
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if (config->data_bus_width == 8) {
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data->single_port = true;
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data->data_port = config->data[0].port;
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for (int i = 1; i < config->data_bus_width; i++) {
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if (data->data_port != config->data[i].port) {
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data->single_port = false;
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}
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}
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}
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if (data->single_port) {
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LOG_DBG("LUT optimization enabled. data_mask=0x%x", config->data_mask);
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}
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#endif
271+
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return ret;
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fail:
274+
LOG_ERR("Failed to configure %s GPIO pin.", failed_pin);
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return ret;
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}
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static const struct mipi_dbi_driver_api mipi_dbi_bitbang_driver_api = {
279+
.reset = mipi_dbi_bitbang_reset,
280+
.command_write = mipi_dbi_bitbang_command_write,
281+
.write_display = mipi_dbi_bitbang_write_display
282+
};
283+
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/* This macro is repeatedly called by LISTIFY() at compile-time to generate the data bus LUT */
285+
#define LUT_GEN(i, n) (((i & (1 << 0)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 0)) : 0) | \
286+
((i & (1 << 1)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 1)) : 0) | \
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((i & (1 << 2)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 2)) : 0) | \
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((i & (1 << 3)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 3)) : 0) | \
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((i & (1 << 4)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 4)) : 0) | \
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((i & (1 << 5)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 5)) : 0) | \
291+
((i & (1 << 6)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 6)) : 0) | \
292+
((i & (1 << 7)) ? (1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 7)) : 0))
293+
294+
/* If at least one instance has an 8-bit bus, add a data look-up table to the read-only config.
295+
* Whether or not it is valid and actually used for a particular instance is decided at runtime
296+
* and stored in the instance's mipi_dbi_bitbang_data.single_port.
297+
*/
298+
#if MIPI_DBI_8_BIT_MODE
299+
#define DATA_LUT_OPTIMIZATION(n) \
300+
.data_lut = { LISTIFY(256, LUT_GEN, (,), n) }, \
301+
.data_mask = ((1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 0)) | \
302+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 1)) | \
303+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 2)) | \
304+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 3)) | \
305+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 4)) | \
306+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 5)) | \
307+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 6)) | \
308+
(1 << DT_INST_GPIO_PIN_BY_IDX(n, data_gpios, 7)))
309+
#else
310+
#define DATA_LUT_OPTIMIZATION(n)
311+
#endif
312+
313+
#define MIPI_DBI_BITBANG_INIT(n) \
314+
static const struct mipi_dbi_bitbang_config mipi_dbi_bitbang_config_##n = { \
315+
.data = {GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 0, {0}), \
316+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 1, {0}), \
317+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 2, {0}), \
318+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 3, {0}), \
319+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 4, {0}), \
320+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 5, {0}), \
321+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 6, {0}), \
322+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 7, {0}), \
323+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 8, {0}), \
324+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 9, {0}), \
325+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 10, {0}), \
326+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 11, {0}), \
327+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 12, {0}), \
328+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 13, {0}), \
329+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 14, {0}), \
330+
GPIO_DT_SPEC_INST_GET_BY_IDX_OR(n, data_gpios, 15, {0})}, \
331+
.data_bus_width = DT_INST_PROP_LEN(n, data_gpios), \
332+
.rd = GPIO_DT_SPEC_INST_GET_OR(n, rd_gpios, {}), \
333+
.wr = GPIO_DT_SPEC_INST_GET_OR(n, wr_gpios, {}), \
334+
.e = GPIO_DT_SPEC_INST_GET_OR(n, e_gpios, {}), \
335+
.cs = GPIO_DT_SPEC_INST_GET_OR(n, cs_gpios, {}), \
336+
.cmd_data = GPIO_DT_SPEC_INST_GET_OR(n, dc_gpios, {}), \
337+
.reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \
338+
DATA_LUT_OPTIMIZATION(n) \
339+
}; \
340+
BUILD_ASSERT(DT_INST_PROP_LEN(n, data_gpios) < MIPI_DBI_MAX_DATA_BUS_WIDTH, \
341+
"Number of data GPIOs in DT exceeds MIPI_DBI_MAX_DATA_BUS_WIDTH"); \
342+
static struct mipi_dbi_bitbang_data mipi_dbi_bitbang_data_##n; \
343+
DEVICE_DT_INST_DEFINE(n, mipi_dbi_bitbang_init, NULL, &mipi_dbi_bitbang_data_##n, \
344+
&mipi_dbi_bitbang_config_##n, POST_KERNEL, \
345+
CONFIG_MIPI_DBI_INIT_PRIORITY, &mipi_dbi_bitbang_driver_api);
346+
347+
DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_BITBANG_INIT)

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