arch: arm: Separate common swap code

There are too many differences between Cortex-A/R and Cortex-M on swap
code. For reducing the complexity and easier to maintain, this commit
introduces the following major changes

  1. Separate swap.c and swap_helper.S into two different parts based on
    the architecture.

  2. Rename 'z_arm_pendsv' to 'z_arm_do_swap' for Cortex-A/R.

  3. Removes the part related to the option 'CONFIG_BUILTIN_STACK_GUARD'
    in 'cortex_a_r/swap_helper.S' because this code is written for
    the Cortex-M architecture.

Signed-off-by: Huifeng Zhang <[email protected]>

Author: SgrrZhf

arch/arm/core/CMakeLists.txt

@@ -9,8 +9,6 @@ zephyr_library_sources(
   nmi.c
   nmi_on_reset.S
   prep_c.c
-  swap.c
-  swap_helper.S
   thread.c
 )
 

arch/arm/core/cortex_a_r/CMakeLists.txt

@@ -12,6 +12,8 @@ zephyr_library_sources(
   stacks.c
   tcm.c
   vector_table.S
+  swap.c
+  swap_helper.S
   )
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c)

arch/arm/core/cortex_a_r/exc_exit.S

@@ -23,7 +23,7 @@ _ASM_FILE_PROLOGUE
 
 GTEXT(z_arm_exc_exit)
 GTEXT(z_arm_int_exit)
-GTEXT(z_arm_pendsv)
+GTEXT(z_arm_do_swap)
 GDATA(_kernel)
 
 .macro userspace_exc_exit
@@ -148,7 +148,7 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
 	ldr r1, [r3, #_kernel_offset_to_current]
 	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
 	cmp r0, r1
-	blne z_arm_pendsv
+	blne z_arm_do_swap
 __EXIT_INT:
 #endif /* CONFIG_PREEMPT_ENABLED */
 
@@ -231,12 +231,12 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)
 	/*
 	 * Switch in the next scheduled thread.
 	 *
-	 * Note that z_arm_pendsv must be called in the SVC mode because it
+	 * Note that z_arm_do_swap must be called in the SVC mode because it
 	 * switches to the SVC mode during context switch and returns to the
 	 * caller using lr_svc.
 	 */
 	cps #MODE_SVC
-	bl z_arm_pendsv
+	bl z_arm_do_swap
 
 	/* Decrement exception nesting count */
 	ldr r3, =_kernel

arch/arm/core/cortex_a_r/swap.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018 Linaro, Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <kernel_internal.h>
+
+extern const int _k_neg_eagain;
+
+/* The 'key' actually represents the BASEPRI register
+ * prior to disabling interrupts via the BASEPRI mechanism.
+ *
+ * arch_swap() itself does not do much.
+ */
+int arch_swap(unsigned int key)
+{
+	/* store off key and return value */
+	_current->arch.basepri = key;
+	_current->arch.swap_return_value = _k_neg_eagain;
+
+	z_arm_cortex_r_svc();
+	irq_unlock(key);
+
+	/* Context switch is performed here. Returning implies the
+	 * thread has been context-switched-in again.
+	 */
+	return _current->arch.swap_return_value;
+}