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10 | 10 |
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11 | 11 | #include <mem.h> |
12 | 12 | #include <zephyr/dt-bindings/clock/rx_clock.h> |
| 13 | +#include <zephyr/dt-bindings/pwm/rx_mtu_pwm.h> |
13 | 14 | #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h> |
14 | 15 |
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15 | 16 | / { |
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599 | 600 | }; |
600 | 601 | }; |
601 | 602 |
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| 603 | + mtu2a: mtu@88680 { |
| 604 | + /* MTUs 0-5 share the same TSTR and TSYR */ |
| 605 | + compatible = "renesas,rx-mtu2a"; |
| 606 | + #address-cells = <1>; |
| 607 | + #size-cells = <1>; |
| 608 | + reg = <0x00088680 0x01>, <0x00088681 0x01>; |
| 609 | + reg-names = "TSTR", "TSYR"; |
| 610 | + |
| 611 | + mtu0: mtu0@88700 { |
| 612 | + compatible = "renesas,rx-mtu"; |
| 613 | + channel = <0>; |
| 614 | + interrupts = <114 1>, <115 1>, <116 1>, <117 3>, <118 4>; |
| 615 | + interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; |
| 616 | + clocks = <&pclkb MSTPA 9>; |
| 617 | + reg-names = "TCR", "TMDR", "TIOR", "TIER", |
| 618 | + "TSR", "TGR", "TCNT", "NFCR"; |
| 619 | + reg = <0x00088700 0x01>, |
| 620 | + <0x00088701 0x01>, |
| 621 | + <0x00088702 0x02>, |
| 622 | + <0x00088704 0x01>, |
| 623 | + <0x00088705 0x01>, |
| 624 | + <0x00088708 0x8>, |
| 625 | + <0x00088706 0x02>, |
| 626 | + <0x00088690 0x01>; |
| 627 | + bit-idx = <0>; |
| 628 | + |
| 629 | + pwm { |
| 630 | + compatible = "renesas,rx-mtu-pwm"; |
| 631 | + prescaler = <RX_MTU_PWM_SOURCE_DIV_16>; |
| 632 | + #pwm-cells = <3>; |
| 633 | + status = "disabled"; |
| 634 | + }; |
| 635 | + }; |
| 636 | + |
| 637 | + mtu1: mtu1@88780 { |
| 638 | + compatible = "renesas,rx-mtu"; |
| 639 | + channel = <1>; |
| 640 | + interrupts = <121 1>, <122 1>, <123 1>; |
| 641 | + interrupt-names = "tgia", "tgib", "tgiv"; |
| 642 | + clocks = <&pclkb MSTPA 9>; |
| 643 | + reg = <0x00088780 0x01>, |
| 644 | + <0x00088781 0x01>, |
| 645 | + <0x00088782 0x01>, |
| 646 | + <0x00088784 0x01>, |
| 647 | + <0x00088785 0x01>, |
| 648 | + <0x00088788 0x4>, |
| 649 | + <0x00088786 0x02>, |
| 650 | + <0x00088691 0x01>; |
| 651 | + reg-names = "TCR", "TMDR", "TIOR", "TIER", |
| 652 | + "TSR", "TGR", "TCNT", "NFCR"; |
| 653 | + bit-idx = <1>; |
| 654 | + |
| 655 | + pwm { |
| 656 | + compatible = "renesas,rx-mtu-pwm"; |
| 657 | + prescaler = <RX_MTU_PWM_SOURCE_DIV_16>; |
| 658 | + #pwm-cells = <3>; |
| 659 | + status = "disabled"; |
| 660 | + }; |
| 661 | + }; |
| 662 | + |
| 663 | + mtu2: mtu2@88800 { |
| 664 | + compatible = "renesas,rx-mtu"; |
| 665 | + channel = <2>; |
| 666 | + interrupts = <125 1>, <126 1>, <127 1>; |
| 667 | + interrupt-names = "tgia", "tgib", "tgiv"; |
| 668 | + clocks = <&pclkb MSTPA 9>; |
| 669 | + reg = <0x00088800 0x01>, |
| 670 | + <0x00088801 0x01>, |
| 671 | + <0x00088802 0x01>, |
| 672 | + <0x00088804 0x01>, |
| 673 | + <0x00088805 0x01>, |
| 674 | + <0x00088808 0x4>, |
| 675 | + <0x00088806 0x02>, |
| 676 | + <0x00088692 0x01>; |
| 677 | + reg-names = "TCR", "TMDR", "TIOR", "TIER", |
| 678 | + "TSR", "TGR", "TCNT", "NFCR"; |
| 679 | + bit-idx = <2>; |
| 680 | + |
| 681 | + pwm { |
| 682 | + compatible = "renesas,rx-mtu-pwm"; |
| 683 | + prescaler = <RX_MTU_PWM_SOURCE_DIV_1>; |
| 684 | + #pwm-cells = <3>; |
| 685 | + status = "disabled"; |
| 686 | + }; |
| 687 | + }; |
| 688 | + |
| 689 | + mtu3: mtu3@88600 { |
| 690 | + compatible = "renesas,rx-mtu"; |
| 691 | + channel = <3>; |
| 692 | + interrupts = <129 1>, <130 1>, <131 1>, <132 1>, <133 1>; |
| 693 | + interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; |
| 694 | + clocks = <&pclkb MSTPA 9>; |
| 695 | + reg = <0x00088600 0x01>, |
| 696 | + <0x00088602 0x01>, |
| 697 | + <0x00088604 0x02>, |
| 698 | + <0x00088608 0x01>, |
| 699 | + <0x0008862c 0x1>, |
| 700 | + <0x00088618 0x8>, |
| 701 | + <0x00088610 0x02>, |
| 702 | + <0x00088693 0x01>; |
| 703 | + reg-names = "TCR", "TMDR", "TIOR", "TIER", |
| 704 | + "TSR", "TGR", "TCNT", "NFCR"; |
| 705 | + bit-idx = <6>; |
| 706 | + |
| 707 | + pwm { |
| 708 | + compatible = "renesas,rx-mtu-pwm"; |
| 709 | + prescaler = <RX_MTU_PWM_SOURCE_DIV_1>; |
| 710 | + #pwm-cells = <3>; |
| 711 | + status = "disabled"; |
| 712 | + }; |
| 713 | + }; |
| 714 | + |
| 715 | + mtu4: mtu4@88601 { |
| 716 | + compatible = "renesas,rx-mtu"; |
| 717 | + channel = <4>; |
| 718 | + interrupts = <134 1>, <135 1>, <136 1>, <137 1>, <138 1>; |
| 719 | + interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; |
| 720 | + clocks = <&pclkb MSTPA 9>; |
| 721 | + reg = <0x00088601 0x01>, |
| 722 | + <0x00088603 0x01>, |
| 723 | + <0x00088606 0x02>, |
| 724 | + <0x00088609 0x01>, |
| 725 | + <0x0008862c 0x1>, |
| 726 | + <0x0008861c 0x8>, |
| 727 | + <0x00088612 0x02>, |
| 728 | + <0x00088694 0x01>; |
| 729 | + reg-names = "TCR", "TMDR", "TIOR", "TIER", |
| 730 | + "TSR", "TGR", "TCNT", "NFCR"; |
| 731 | + bit-idx = <7>; |
| 732 | + |
| 733 | + pwm { |
| 734 | + compatible = "renesas,rx-mtu-pwm"; |
| 735 | + prescaler = <RX_MTU_PWM_SOURCE_DIV_1>; |
| 736 | + #pwm-cells = <3>; |
| 737 | + status = "disabled"; |
| 738 | + }; |
| 739 | + }; |
| 740 | + }; |
| 741 | + |
602 | 742 | sci9: sci9@8a120 { |
603 | 743 | compatible = "renesas,rx-sci"; |
604 | 744 | interrupts = <235 1>, <236 1>, <237 1>, <234 1>; |
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