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1 parent c86f0ac commit 27c2c62Copy full SHA for 27c2c62
dts/arm/st/wb0/stm32wb0.dtsi
@@ -218,6 +218,22 @@
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status = "disabled";
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};
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+ adc1: adc@41006000 {
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+ compatible = "st,stm32wb0-adc";
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+ reg = <0x41006000 256>;
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+ /* On STM32WB0, the two ADC clock domains (ANALOG / DIGITAL)
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+ * can be controlled independently. Expose this feature to
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+ * the driver by having two `clocks` property entries:
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+ * - first entry is digital part of ADC block (always-on)
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+ * - second entry is analog part of ADC block (on-demand)
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+ */
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+ clocks = <&rcc STM32_CLOCK(APB1, 4)>,
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+ <&rcc STM32_CLOCK(APB1, 5)>;
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+ interrupts = <12 0>;
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+ #io-channel-cells = <1>;
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+ status = "disabled";
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+ };
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+
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dma1: dma@48700000 {
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compatible = "st,stm32-dma-v2bis";
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#dma-cells = <2>;
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