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boards: renesas: enable support for SDRAM on ek_ra8d1 board
Add support for SDRAM on Renesas RA EK-RA8D1 Signed-off-by: The Nguyen <[email protected]>
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‎boards/renesas/ek_ra8d1/CMakeLists.txt

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_linker_sources_ifdef(CONFIG_MEMC
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SECTIONS sdram.ld)

‎boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi

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renesas,analog-enable;
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};
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};
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sdram_default: sdram_default{
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group1 {
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/* SDRAM_DQM1 */
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psels = <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
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/* SDRAM_CKE */
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<RA_PSEL(RA_PSEL_BUS, 1, 13)>,
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/* SDRAM_WE */
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<RA_PSEL(RA_PSEL_BUS, 1, 14)>,
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/* SDRAM_CS */
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<RA_PSEL(RA_PSEL_BUS, 1, 15)>,
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/* SDRAM_A0 */
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<RA_PSEL(RA_PSEL_BUS, 3, 0)>,
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/* SDRAM_A1 */
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<RA_PSEL(RA_PSEL_BUS, 3, 1)>,
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/* SDRAM_A2 */
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<RA_PSEL(RA_PSEL_BUS, 3, 2)>,
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/* SDRAM_A3 */
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<RA_PSEL(RA_PSEL_BUS, 3, 3)>,
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/* SDRAM_A4 */
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<RA_PSEL(RA_PSEL_BUS, 3, 4)>,
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/* SDRAM_A5 */
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<RA_PSEL(RA_PSEL_BUS, 3, 5)>,
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/* SDRAM_A6 */
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<RA_PSEL(RA_PSEL_BUS, 3, 6)>,
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/* SDRAM_A7 */
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<RA_PSEL(RA_PSEL_BUS, 3, 7)>,
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/* SDRAM_A8 */
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<RA_PSEL(RA_PSEL_BUS, 3, 8)>,
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/* SDRAM_A9 */
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<RA_PSEL(RA_PSEL_BUS, 3, 9)>,
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/* SDRAM_A10 */
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<RA_PSEL(RA_PSEL_BUS, 3, 10)>,
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/* SDRAM_A11 */
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<RA_PSEL(RA_PSEL_BUS, 3, 11)>,
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/* SDRAM_A12 */
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<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
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/* SDRAM_D0 */
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<RA_PSEL(RA_PSEL_BUS, 6, 1)>,
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/* SDRAM_D1 */
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<RA_PSEL(RA_PSEL_BUS, 6, 2)>,
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/* SDRAM_D2 */
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<RA_PSEL(RA_PSEL_BUS, 6, 3)>,
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/* SDRAM_D3 */
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<RA_PSEL(RA_PSEL_BUS, 6, 4)>,
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/* SDRAM_D4 */
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<RA_PSEL(RA_PSEL_BUS, 6, 5)>,
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/* SDRAM_D5 */
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<RA_PSEL(RA_PSEL_BUS, 6, 6)>,
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/* SDRAM_D6 */
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<RA_PSEL(RA_PSEL_BUS, 6, 7)>,
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/* SDRAM_D8 */
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<RA_PSEL(RA_PSEL_BUS, 6, 9)>,
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/* SDRAM_D9 */
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<RA_PSEL(RA_PSEL_BUS, 6, 10)>,
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/* SDRAM_D10 */
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<RA_PSEL(RA_PSEL_BUS, 6, 11)>,
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/* SDRAM_D11 */
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<RA_PSEL(RA_PSEL_BUS, 6, 12)>,
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/* SDRAM_D12 */
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<RA_PSEL(RA_PSEL_BUS, 6, 13)>,
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/* SDRAM_D13 */
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<RA_PSEL(RA_PSEL_BUS, 6, 14)>,
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/* SDRAM_D14 */
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<RA_PSEL(RA_PSEL_BUS, 6, 15)>,
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/* SDRAM_BA0 */
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<RA_PSEL(RA_PSEL_BUS, 9, 5)>,
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/* SDRAM_BA1 */
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<RA_PSEL(RA_PSEL_BUS, 9, 6)>,
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/* SDRAM_RAS */
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<RA_PSEL(RA_PSEL_BUS, 9, 8)>,
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/* SDRAM_CAS */
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<RA_PSEL(RA_PSEL_BUS, 9, 9)>,
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/* SDRAM_SDCLK */
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<RA_PSEL(RA_PSEL_BUS, 10, 9)>;
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drive-strength = "high";
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};
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group2 {
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/* SDRAM_SDCLK */
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psels = <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
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drive-strength = "highspeed-high";
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};
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group3 {
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/* SDRAM_D7 */
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psels = <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
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/* SDRAM_D15 */
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<RA_PSEL(RA_PSEL_BUS, 10, 8)>,
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/* SDRAM_DQM0 */
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<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
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};
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};
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};

‎boards/renesas/ek_ra8d1/ek_ra8d1.dts

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#include <renesas/ra/ra8/r7fa8d1bhecbd.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input-event-codes.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include "ek_ra8d1-pinctrl.dtsi"
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};
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};
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sdram1: sdram@68000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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device_type = "memory";
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reg = <0x68000000 DT_SIZE_M(64)>; /* 512 Mbits */
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zephyr,memory-region = "SDRAM";
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status = "okay";
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};
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aliases {
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led0 = &led1;
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sw0 = &button0;
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interrupts = <89 12>;
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status = "okay";
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};
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&sdram {
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pinctrl-0 = <&sdram_default>;
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pinctrl-names = "default";
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status = "okay";
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auto-refresh-interval = <SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES>;
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auto-refresh-count = <SDRAM_AUTO_REFREDSH_COUNT_8TIMES>;
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precharge-cycle-count = <SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES>;
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multiplex-addr-shift = "10-bit";
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edian-mode = "little-endian";
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continuous-access;
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bus-width = "16-bit";
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bank@0 {
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reg = <0>;
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renesas,ra-sdram-timing = <SDRAM_TRAS_6CYCLES
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SDRAM_TRCD_3CYCLES
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SDRAM_TRP_3CYCLES
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SDRAM_TWR_2CYCLES
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SDRAM_TCL_3CYCLES
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937
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SDRAM_TREFW_8CYCLES>;
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};
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};

‎boards/renesas/ek_ra8d1/sdram.ld

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)
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SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),)
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{
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__SDRAM_Start = .;
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KEEP(*(.sdram*))
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__SDRAM_End = .;
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} GROUP_LINK_IN(SDRAM)
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#endif

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