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driver: gd32e1: drop unnessary code in gpio driver
drop unnessary code in gpio driver. Signed-off-by: YuLong Yao <[email protected]>
1 parent 90840f8 commit 282622d

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2 files changed

+12
-135
lines changed

2 files changed

+12
-135
lines changed

‎drivers/gpio/gpio_gd32.c‎

Lines changed: 10 additions & 123 deletions
Original file line numberDiff line numberDiff line change
@@ -16,100 +16,12 @@
1616
#include <pinmux/pinmux_gd32.h>
1717
#include <drivers/pinmux.h>
1818
#include <sys/util.h>
19-
// #include <drivers/interrupt_controller/exti_gd32.h>
2019
#include <pm/device.h>
2120
#include <pm/device_runtime.h>
2221

23-
// #include "gd32_hsem.h"
2422
#include "gpio_gd32.h"
2523
#include "gpio_utils.h"
2624

27-
/**
28-
* @brief Common GPIO driver for gd32 MCUs.
29-
*/
30-
31-
/**
32-
* @brief EXTI interrupt callback
33-
*/
34-
// static void gpio_gd32_isr(int line, void *arg)
35-
// {
36-
// struct gpio_gd32_data *data = arg;
37-
38-
// gpio_fire_callbacks(&data->cb, data->dev, BIT(line));
39-
// }
40-
41-
/**
42-
* @brief Common gpio flags to custom flags
43-
*/
44-
// static int gpio_gd32_flags_to_conf(int flags, int *pincfg)
45-
// {
46-
47-
// if ((flags & GPIO_OUTPUT) != 0) {
48-
// /* Output only or Output/Input */
49-
50-
// *pincfg = gd32_PINCFG_MODE_OUTPUT;
51-
52-
// if ((flags & GPIO_SINGLE_ENDED) != 0) {
53-
// if (flags & GPIO_LINE_OPEN_DRAIN) {
54-
// *pincfg |= gd32_PINCFG_OPEN_DRAIN;
55-
// } else {
56-
// /* Output can't be open source */
57-
// return -ENOTSUP;
58-
// }
59-
// } else {
60-
// *pincfg |= gd32_PINCFG_PUSH_PULL;
61-
// }
62-
63-
// if ((flags & GPIO_PULL_UP) != 0) {
64-
// *pincfg |= gd32_PINCFG_PULL_UP;
65-
// } else if ((flags & GPIO_PULL_DOWN) != 0) {
66-
// *pincfg |= gd32_PINCFG_PULL_DOWN;
67-
// }
68-
69-
// } else if ((flags & GPIO_INPUT) != 0) {
70-
// /* Input */
71-
72-
// *pincfg = gd32_PINCFG_MODE_INPUT;
73-
74-
// if ((flags & GPIO_PULL_UP) != 0) {
75-
// *pincfg |= gd32_PINCFG_PULL_UP;
76-
// } else if ((flags & GPIO_PULL_DOWN) != 0) {
77-
// *pincfg |= gd32_PINCFG_PULL_DOWN;
78-
// } else {
79-
// *pincfg |= gd32_PINCFG_FLOATING;
80-
// }
81-
// } else {
82-
// /* Desactivated: Analog */
83-
// *pincfg = gd32_PINCFG_MODE_ANALOG;
84-
// }
85-
86-
// return 0;
87-
// }
88-
89-
/**
90-
* @brief Translate pin to pinval that the LL library needs
91-
*/
92-
static inline uint32_t gd32_pinval_get(int pin)
93-
{
94-
uint32_t pinval;
95-
96-
#ifdef CONFIG_SOC_SERIES_gd32F1X
97-
pinval = (1 << pin) << GPIO_PIN_MASK_POS;
98-
if (pin < 8) {
99-
pinval |= 1 << pin;
100-
} else {
101-
pinval |= (1 << (pin % 8)) | 0x04000000;
102-
}
103-
#else
104-
pinval = 1 << pin;
105-
#endif
106-
return pinval;
107-
}
108-
109-
uint32_t test(uint32_t a){
110-
return a+1;
111-
}
112-
11325
/**
11426
* @brief Configure the hardware.
11527
*/
@@ -155,26 +67,6 @@ static inline uint32_t gpio_gd32_pin_to_exti_line(int pin)
15567
return 0;
15668
}
15769

158-
// static void gpio_gd32_set_exti_source(int port, int pin)
159-
// {
160-
161-
// }
162-
163-
// static int gpio_gd32_get_exti_source(int pin)
164-
// {
165-
166-
// return 0;
167-
// }
168-
169-
/**
170-
* @brief Enable EXTI of the specific line
171-
*/
172-
// static int gpio_gd32_enable_int(int port, int pin)
173-
// {
174-
175-
// return 0;
176-
// }
177-
17870
static int gpio_gd32_port_get_raw(const struct device *dev, uint32_t *value)
17971
{
18072

@@ -185,8 +77,6 @@ static int gpio_gd32_port_set_masked_raw(const struct device *dev,
18577
gpio_port_pins_t mask,
18678
gpio_port_value_t value)
18779
{
188-
189-
19080
return 0;
19181
}
19282

@@ -225,10 +115,8 @@ static int gpio_gd32_config(const struct device *dev,
225115
int err = 0;
226116
int pincfg = 0;
227117

228-
int i = 0;
229-
i++;
230-
231-
/* todo: figure out if we can map the requested GPIO
118+
// todo:
119+
/* figure out if we can map the requested GPIO
232120
* configuration
233121
*/
234122
// err = gpio_gd32_flags_to_conf(flags, &pincfg);
@@ -255,7 +143,6 @@ static int gpio_gd32_pin_interrupt_configure(const struct device *dev,
255143
enum gpio_int_mode mode,
256144
enum gpio_int_trig trig)
257145
{
258-
259146
return 0;
260147
}
261148

@@ -307,11 +194,11 @@ static int gpio_gd32_pm_device_ctrl(const struct device *dev,
307194

308195

309196
#define GPIO_DEVICE_INIT(__node, __suffix, __base_addr, __port, __cenr, __bus) \
310-
static const struct gpio_gd32_config gpio_gd32_cfg_## __suffix = { \
197+
static const struct gpio_gd32_config gpio_gd32_cfg_## __suffix = { \
311198
.common = { \
312199
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
313200
}, \
314-
.base = (uint32_t *)__base_addr, \
201+
.base = (uint32_t *)__base_addr, \
315202
.port = __port, \
316203
.pclken = { .bus = __bus, .enr = __cenr } \
317204
}; \
@@ -320,16 +207,16 @@ static int gpio_gd32_pm_device_ctrl(const struct device *dev,
320207
gpio_gd32_init, \
321208
gpio_gd32_pm_device_ctrl, \
322209
&gpio_gd32_data_## __suffix, \
323-
&gpio_gd32_cfg_## __suffix, \
210+
&gpio_gd32_cfg_## __suffix, \
324211
POST_KERNEL, \
325212
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
326213
&gpio_gd32_driver)
327214

328-
#define GPIO_DEVICE_INIT_GD32(__suffix, __SUFFIX) \
329-
GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), \
330-
__suffix, \
331-
DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)), \
332-
GD32_PORT##__SUFFIX, \
215+
#define GPIO_DEVICE_INIT_GD32(__suffix, __SUFFIX) \
216+
GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), \
217+
__suffix, \
218+
DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)), \
219+
GD32_PORT##__SUFFIX, \
333220
DT_CLOCKS_CELL(DT_NODELABEL(gpio##__suffix), bits),\
334221
DT_CLOCKS_CELL(DT_NODELABEL(gpio##__suffix), bus))
335222

‎drivers/gpio/gpio_gd32.h‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -11,24 +11,14 @@
1111
* @file header for GD32 GPIO
1212
*/
1313

14-
#include <drivers/clock_control/stm32_clock_control.h>
14+
#include <drivers/clock_control/gd32_clock_control.h>
1515
#include <pinmux/pinmux_gd32.h>
1616
#include <drivers/gpio.h>
1717

1818
/* GPIO buses definitions */
1919

2020
#define GD32_PORT_NOT_AVAILABLE 0xFFFFFFFF
2121

22-
#ifdef CONFIG_SOC_SERIES_GD32E1X
23-
#define GD32_CLOCK_BUS_GPIO GD32_CLOCK_BUS_AHB1
24-
#define GD32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
25-
#define GD32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
26-
#define GD32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
27-
#define GD32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
28-
#define GD32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
29-
#define GD32_PERIPH_GPIOAF AFIO
30-
#endif /* CONFIG_SOC_SERIES_* */
31-
3222
/**
3323
* @brief configuration of GPIO device
3424
*/
@@ -39,7 +29,7 @@ struct gpio_gd32_config {
3929
uint32_t *base;
4030
/* IO port */
4131
int port;
42-
struct stm32_pclken pclken;
32+
struct gd32_pclken pclken;
4333
};
4434

4535
/**

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