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| 1 | +# Kconfig - XTENSA architecture configuration options |
| 2 | +# |
| 3 | +# Copyright (c) 2016 Cadence Design Systems, Inc. |
| 4 | +# SPDX-License-Identifier: Apache-2.0 |
| 5 | + |
| 6 | +choice |
| 7 | + prompt "XTENSA core Selection" |
| 8 | + default sample_controller |
| 9 | + depends on XTENSA |
| 10 | + |
| 11 | +source "arch/xtensa/soc/Kconfig.cores" |
| 12 | +endchoice |
| 13 | + |
| 14 | +menu "XTENSA Options" |
| 15 | + depends on XTENSA |
| 16 | + |
| 17 | +config ARCH |
| 18 | + default "xtensa" |
| 19 | + |
| 20 | +config SYS_CLOCK_HW_CYCLES_PER_SEC |
| 21 | + int |
| 22 | + prompt "Hardware clock cycles per second, 2000000 for ISS" |
| 23 | + default 2000000 |
| 24 | + range 1000000 1000000000 |
| 25 | + help |
| 26 | + This option specifies hardware clock. |
| 27 | + |
| 28 | +config XTENSA_NO_IPC |
| 29 | + bool "Core has no IPC support" |
| 30 | + select ATOMIC_OPERATIONS_C |
| 31 | + default n |
| 32 | + help |
| 33 | + Uncheck this if you core does not implment "SCOMPARE1" register and "s32c1i" |
| 34 | + isntruction. |
| 35 | + |
| 36 | +config SW_ISR_TABLE |
| 37 | + bool |
| 38 | + prompt "Enable software interrupt handler table" |
| 39 | + default y |
| 40 | + help |
| 41 | + Enable an interrupt handler table implemented in software. This |
| 42 | + table, unlike ISRs connected directly in the vector table, allow |
| 43 | + a parameter to be passed to the interrupt handlers. Also, invoking |
| 44 | + the exeception/interrupt exit stub is automatically done. |
| 45 | + This has to be enabled for dynamically connecting interrupt handlers |
| 46 | + at runtime (SW_ISR_TABLE_DYNAMIC). |
| 47 | + |
| 48 | +config IRQ_OFFLOAD |
| 49 | + bool "Enable IRQ offload" |
| 50 | + default n |
| 51 | + help |
| 52 | + Enable irq_offload() API which allows functions to be synchronously |
| 53 | + run in interrupt context. Uses one entry in the IDT. Mainly useful |
| 54 | + for test cases. |
| 55 | + |
| 56 | +config SW_ISR_TABLE_DYNAMIC |
| 57 | + bool |
| 58 | + prompt "Allow installing interrupt handlers at runtime" |
| 59 | + depends on SW_ISR_TABLE |
| 60 | + default n |
| 61 | + help |
| 62 | + This option enables irq_connect_dynamic(). It moves the ISR table to |
| 63 | + SRAM so that it is writable. This has the side-effect of removing |
| 64 | + write-protection on the ISR table. |
| 65 | + |
| 66 | +menu "Specific core configuration" |
| 67 | + |
| 68 | +config IRQ_OFFLOAD_INTNUM |
| 69 | + int |
| 70 | + prompt "IRQ offload SW interrupt index" |
| 71 | + help |
| 72 | + The index of the software interrupt to be used for IRQ offload. |
| 73 | + |
| 74 | + Please note that in order for IRQ offload to work correctly the selected |
| 75 | + interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL. |
| 76 | + |
| 77 | +source "arch/xtensa/soc/*/Kconfig" |
| 78 | + |
| 79 | +endmenu |
| 80 | + |
| 81 | +endmenu |
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