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drivers: serial: bouffalolab: Add bflb serial driver
Add Bouffalo Lab serial driver. The driver uses pinctrl to configure pins and have power management capabilities. Signed-off-by: Gerson Fernando Budke <[email protected]>
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‎drivers/serial/CMakeLists.txt‎

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@@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
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zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)
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zephyr_library_sources_ifdef(CONFIG_UART_APBUART uart_apbuart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BFLB uart_bflb.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BT uart_bt.c)
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zephyr_library_sources_ifdef(CONFIG_UART_CC13XX_CC26XX uart_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_CC32XX uart_cc32xx.c)

‎drivers/serial/Kconfig‎

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@@ -229,6 +229,8 @@ rsource "Kconfig.xlnx"
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rsource "Kconfig.xmc4xxx"
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# zephyr-keep-sorted-stop
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rsource "Kconfig.bflb"
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source "drivers/serial/Kconfig.si32"
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source "drivers/serial/Kconfig.wch_usart"

‎drivers/serial/Kconfig.bflb‎

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# Copyright (c) 2021-2025 ATL Electronics
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#
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# SPDX-License-Identifier: Apache-2.0
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config UART_BFLB
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bool "Bouffalo Lab serial driver"
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depends on DT_HAS_BFLB_UART_ENABLED
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select PINCTRL
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select SERIAL_HAS_DRIVER
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select USE_BFLB_UART
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help
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This option enables the UART driver for Bouffalo Lab SoC family.

‎drivers/serial/uart_bflb.c‎

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/*
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* Copyright (c) 2021-2025 ATL Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT bflb_uart
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/**
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* @brief UART driver for Bouffalo Lab MCU family.
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*/
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/pm/device.h>
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#include <soc.h>
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#include <bflb_pinctrl.h>
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#include <bflb_uart.h>
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#include <bflb_glb.h>
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#define UART_CTS_FLOWCONTROL_ENABLE (0)
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#define UART_RTS_FLOWCONTROL_ENABLE (0)
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#define UART_MSB_FIRST_ENABLE (0)
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#define UART_DEFAULT_RTO_TIMEOUT (255)
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#define UART_CLOCK_DIV (0)
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struct blfb_config {
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const struct pinctrl_dev_config *pinctrl_cfg;
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uint32_t periph_id;
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UART_CFG_Type uart_cfg;
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UART_FifoCfg_Type fifo_cfg;
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};
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static int uart_blfb_init(const struct device *dev)
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{
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const struct blfb_config *cfg = dev->config;
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pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT);
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GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, UART_CLOCK_DIV);
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UART_IntMask(cfg->periph_id, UART_INT_ALL, 1);
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UART_Disable(cfg->periph_id, UART_TXRX);
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UART_Init(cfg->periph_id, (UART_CFG_Type *)&cfg->uart_cfg);
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UART_TxFreeRun(cfg->periph_id, 1);
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UART_SetRxTimeoutValue(cfg->periph_id, UART_DEFAULT_RTO_TIMEOUT);
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UART_FifoConfig(cfg->periph_id, (UART_FifoCfg_Type *)&cfg->fifo_cfg);
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UART_Enable(cfg->periph_id, UART_TXRX);
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return 0;
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}
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static int uart_blfb_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct blfb_config *cfg = dev->config;
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return UART_ReceiveData(cfg->periph_id, (uint8_t *)c, 1) ? 0 : -1;
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}
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static void uart_blfb_poll_out(const struct device *dev, unsigned char c)
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{
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const struct blfb_config *cfg = dev->config;
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while (UART_GetTxFifoCount(cfg->periph_id) == 0) {
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;
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}
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(void)UART_SendData(cfg->periph_id, (uint8_t *)&c, 1);
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}
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#ifdef CONFIG_PM_DEVICE
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static int uart_blfb_pm_control(const struct device *dev,
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enum pm_device_action action)
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{
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const struct blfb_config *cfg = dev->config;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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(void)pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT);
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UART_Enable(cfg->periph_id, UART_TXRX);
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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if (pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_SLEEP)) {
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return -ENOTSUP;
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}
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UART_Disable(cfg->periph_id, UART_TXRX);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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#endif /* CONFIG_PM_DEVICE */
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static DEVICE_API(uart, uart_blfb_driver_api) = {
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.poll_in = uart_blfb_poll_in,
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.poll_out = uart_blfb_poll_out,
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};
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#define BLFB_UART_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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PM_DEVICE_DT_INST_DEFINE(n, uart_blfb_pm_control); \
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static const struct blfb_config blfb_uart##n##_config = { \
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.pinctrl_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.periph_id = DT_INST_PROP(n, peripheral_id), \
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\
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.uart_cfg.baudRate = DT_INST_PROP(n, current_speed), \
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.uart_cfg.dataBits = UART_DATABITS_8, \
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.uart_cfg.stopBits = UART_STOPBITS_1, \
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.uart_cfg.parity = UART_PARITY_NONE, \
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.uart_cfg.uartClk = SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ, \
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.uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE, \
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.uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE, \
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.uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE, \
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\
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.fifo_cfg.txFifoDmaThreshold = 1, \
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.fifo_cfg.rxFifoDmaThreshold = 1, \
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.fifo_cfg.txFifoDmaEnable = 0, \
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.fifo_cfg.rxFifoDmaEnable = 0, \
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}; \
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DEVICE_DT_INST_DEFINE(n, &uart_blfb_init, \
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PM_DEVICE_DT_INST_GET(n), \
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NULL, \
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&blfb_uart##n##_config, PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&uart_blfb_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(BLFB_UART_INIT)

‎dts/bindings/serial/bflb,uart.yaml‎

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# Copyright (c) 2021-2025 ATL Electronics
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Bouffalo Lab UART
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compatible: "bflb,uart"
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include:
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- name: uart-controller.yaml
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- name: pinctrl-device.yaml
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properties:
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reg:
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required: true
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peripheral-id:
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type: int
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description: peripheral ID
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required: true

‎dts/riscv/bouffalolab/bl60x.dtsi‎

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};
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};
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uart0: uart@4000a000 {
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compatible = "bflb,uart";
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reg = <0x4000a000 0x100>;
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peripheral-id = <0>;
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interrupts = <29 0>;
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interrupt-parent = <&ictrl>;
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status = "disabled";
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};
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uart1: uart@4000a100 {
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compatible = "bflb,uart";
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reg = <0x4000a100 0x100>;
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peripheral-id = <1>;
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interrupts = <30 0>;
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interrupt-parent = <&ictrl>;
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status = "disabled";
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};
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spi0: spi@4000a200 {
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compatible = "bflb,spi";
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reg = <0x4000a200 0x100>;

‎modules/hal_bouffalolab/include/bflb_uart.h‎

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/*
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* Copyright (c) 2021-2025 Gerson Fernando Budke <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_HAL_BFLB_UART_H_
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#define ZEPHYR_HAL_BFLB_UART_H_
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#ifdef CONFIG_SOC_SERIES_BL60X
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#include <bl602_uart.h>
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#endif
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#endif /* ZEPHYR_HAL_BFLB_UART_H_ */

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