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nzmichaelhDhiru Kholia
nzmichaelh
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Dhiru Kholia
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drivers: add the gpio driver for wch ch32v003
This commit adds the gpio driver for WCH CH32V003. Signed-off-by: Michael Hope <[email protected]> Signed-off-by: Dhiru Kholia <[email protected]>
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‎drivers/gpio/CMakeLists.txt‎

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@@ -94,6 +94,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_TCA6424A gpio_tca6424a.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TEST gpio_test.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TLE9104 gpio_tle9104.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_WCH_GPIO wch_gpio_ch32v00x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XEC gpio_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XEC_V2 gpio_mchp_xec_v2.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XLNX_AXI gpio_xlnx_axi.c)

‎drivers/gpio/Kconfig‎

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@@ -178,6 +178,7 @@ source "drivers/gpio/Kconfig.sx1509b"
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source "drivers/gpio/Kconfig.tca6424a"
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source "drivers/gpio/Kconfig.test"
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source "drivers/gpio/Kconfig.tle9104"
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source "drivers/gpio/Kconfig.wch_ch32v00x"
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source "drivers/gpio/Kconfig.xec"
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source "drivers/gpio/Kconfig.xlnx"
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source "drivers/gpio/Kconfig.xlnx_ps"

‎drivers/gpio/Kconfig.wch_ch32v00x‎

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# Copyright (c) 2024 Michael Hope
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_WCH_GPIO
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bool "WCH CH32V00x GPIO driver"
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depends on DT_HAS_WCH_GPIO_ENABLED
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default y

‎drivers/gpio/wch_gpio_ch32v00x.c‎

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/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/irq.h>
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#include <ch32_gpio.h>
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#define DT_DRV_COMPAT wch_gpio
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struct gpio_ch32v00x_config {
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struct gpio_driver_config common;
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GPIO_TypeDef *regs;
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const struct device *clock_dev;
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uint8_t clock_id;
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};
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struct gpio_ch32v00x_data {
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struct gpio_driver_data common;
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};
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static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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GPIO_TypeDef *regs = config->regs;
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uint32_t cnf_mode;
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uint32_t bshr = 0;
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if ((flags & GPIO_OUTPUT) != 0) {
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cnf_mode = 0x01;
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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bshr = 1 << pin;
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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bshr = 1 << (16 + pin);
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}
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} else if ((flags & GPIO_INPUT) != 0) {
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if ((flags & GPIO_PULL_UP) != 0) {
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cnf_mode = 0x08;
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bshr = 1 << pin;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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cnf_mode = 0x08;
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bshr = 1 << (16 + pin);
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} else {
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cnf_mode = 0x04;
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}
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} else {
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cnf_mode = 0x00;
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}
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regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin));
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regs->BSHR = bshr;
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return 0;
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}
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static int gpio_ch32v00x_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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*value = config->regs->INDR;
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return 0;
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}
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static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask,
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uint32_t value)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BSHR = ((~value & mask) << 16) | (value & mask);
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return 0;
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}
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static int gpio_ch32v00x_port_set_bits_raw(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BSHR = pins;
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return 0;
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}
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static int gpio_ch32v00x_port_clear_bits_raw(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BCR = pins;
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return 0;
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}
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static int gpio_ch32v00x_port_toggle_bits(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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uint32_t changed = (config->regs->OUTDR ^ pins) & pins;
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config->regs->BSHR = (changed & pins) | (~changed & pins) << 16;
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return 0;
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}
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static const struct gpio_driver_api gpio_ch32v00x_driver_api = {
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.pin_configure = gpio_ch32v00x_configure,
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.port_get_raw = gpio_ch32v00x_port_get_raw,
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.port_set_masked_raw = gpio_ch32v00x_port_set_masked_raw,
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.port_set_bits_raw = gpio_ch32v00x_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ch32v00x_port_clear_bits_raw,
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.port_toggle_bits = gpio_ch32v00x_port_toggle_bits,
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};
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static int gpio_ch32v00x_init(const struct device *dev)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id);
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return 0;
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}
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#define GPIO_CH32V00X_INIT(idx) \
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static const struct gpio_ch32v00x_config gpio_ch32v00x_##idx##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
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}, \
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.regs = (GPIO_TypeDef *)DT_INST_REG_ADDR(idx), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_id = DT_INST_CLOCKS_CELL(idx, id), \
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}; \
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\
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static struct gpio_ch32v00x_data gpio_ch32v00x_##idx##_data; \
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\
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DEVICE_DT_INST_DEFINE(idx, gpio_ch32v00x_init, NULL, &gpio_ch32v00x_##idx##_data, \
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&gpio_ch32v00x_##idx##_config, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_ch32v00x_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_CH32V00X_INIT)

‎dts/bindings/gpio/wch,gpio.yaml‎

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# Copyright (c) 2024 Michael Hope
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# SPDX-License-Identifier: Apache-2.0
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description: WCH CH32V00x General-Purpose Input/Output (GPIO)
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compatible: "wch,gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

‎modules/hal_wch/ch32_gpio.h‎

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/*
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* Copyright (c) 2024 Dhiru Kholia
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CH32_GPIO_H
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#define _CH32_GPIO_H
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#ifdef CONFIG_SOC_CH32V003
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#include <ch32v003fun.h>
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#else
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#error "SoC not supported!"
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#endif
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#endif

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