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dts: stm32: Streamline Devicetree binding descriptions
Ensure consistent (and concise) short descriptions of all the st,*.yaml bindings Signed-off-by: Benjamin Cabé <[email protected]>
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dts/bindings/adc/st,stm32-adc.yaml

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# Copyright (c) 2018, Song Qiang <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: ST STM32 family ADC
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description: STM32 ADC
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compatible: "st,stm32-adc"
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dts/bindings/adc/st,stm32f1-adc.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: |
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ST STM32F1 family ADC
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STM32F1 ADC
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This compatible stands for all ADC blocks similar to the one on STM32F1,
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like STM32F37x.
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Remove the st,adc-clock-source and st,adc-prescaler property.

dts/bindings/adc/st,stm32f4-adc.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: |
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ST STM32F4 family ADC
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STM32F4 ADC
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This compatible stands for all ADC blocks similar to the one on STM32F4,
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like F2, F7 or L1.
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dts/bindings/adc/st,stm32n6-adc.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: |
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ST STM32N6 ADC
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STM32N6 ADC
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This compatible stands for STM32N6 ADC.
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compatible: "st,stm32n6-adc"

dts/bindings/adc/st,stm32wb0-adc.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: STM32WB0 series Analog-to-Digital Converter
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description: STM32WB0 Analog-to-Digital Converter
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compatible: "st,stm32wb0-adc"
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dts/bindings/can/st,stm32-fdcan.yaml

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description: ST STM32 FDCAN CAN FD controller
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description: STM32 FDCAN CAN FD controller
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compatible: "st,stm32-fdcan"
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dts/bindings/can/st,stm32h7-fdcan.yaml

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description: ST STM32H7 series FDCAN CAN FD controller
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description: STM32H7 series FDCAN CAN FD controller
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compatible: "st,stm32h7-fdcan"
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dts/bindings/clock/st,stm32-clock-mux.yaml

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description: |
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STM32 Clock multiplexer
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Describes a clock multiplexer, such as per_ck on STM32H7 or
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CLK48 on STM32WB.
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The only property of this node is to select a clock input.

dts/bindings/clock/st,stm32-rcc.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 Reset and Clock controller node.
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STM32 RCC (Reset and Clock controller).
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This node is in charge of system clock ('SYSCLK') source selection and controlling
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clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
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dts/bindings/clock/st,stm32c0-hsi-clock.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 HSI Clock node description for STM32C0 devices
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STM32C0 HSI Clock.
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On STM32C0, HSI is a 48MHz fixed clock.
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It also produces a HSISYS secondary clk which can be used as system clock

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